Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fsl_lsch3_speed.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index f8fefc7cfc028ec06cbe98faf895a0f50bd5326c..b3e67321b485eb47bbd81f61daf87106e328f2a7 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015, Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ * Copyright 2019 NXP Semiconductors
  *
  * Derived from arch/power/cpu/mpc85xx/speed.c
  */
@@ -26,10 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-       struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-       u32 ccr;
-#endif
        struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
                (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
                (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
@@ -68,6 +64,9 @@ void get_sys_info(struct sys_info *sys_info)
        };
 
        uint i, cluster;
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+       uint rcw_tmp;
+#endif
        uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
        uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
        unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
@@ -128,14 +127,43 @@ void get_sys_info(struct sys_info *sys_info)
        }
 
 #if defined(CONFIG_FSL_IFC)
-       ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-       ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+       sys_info->freq_localbus = sys_info->freq_systembus /
+                                               CONFIG_SYS_FSL_IFC_CLK_DIV;
+#endif
 
-       sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+#define HWA_CGA_M2_CLK_SEL      0x00380000
+#define HWA_CGA_M2_CLK_SHIFT    19
+       rcw_tmp = in_le32(&gur->rcwsr[5]);
+       switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+       case 1:
+               sys_info->freq_cga_m2 = freq_c_pll[1];
+               break;
+       case 2:
+               sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
+               break;
+       case 3:
+               sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
+               break;
+       case 4:
+               sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
+               break;
+       case 6:
+               sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
+               break;
+       case 7:
+               sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
+               break;
+       default:
+               printf("Error: Unknown peripheral clock select!\n");
+               break;
+       }
+#endif
+#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB)
+       sys_info->freq_cga_m2 = sys_info->freq_systembus;
 #endif
 }
 
-
 int get_clocks(void)
 {
        struct sys_info sys_info;
@@ -147,7 +175,16 @@ int get_clocks(void)
        gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 #endif
 #if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB)
+       gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
+#endif
+#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+       gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+#endif
+#else
        gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
+#endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
        if (gd->cpu_clk != 0)
@@ -199,6 +236,16 @@ int get_dspi_freq(ulong dummy)
        return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
 }
 
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+       if (!gd->arch.sdhc_clk)
+               get_clocks();
+
+       return gd->arch.sdhc_clk;
+}
+#endif
+
 int get_serial_clock(void)
 {
        return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
@@ -209,6 +256,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        switch (clk) {
        case MXC_I2C_CLK:
                return get_i2c_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+       case MXC_ESDHC_CLK:
+       case MXC_ESDHC2_CLK:
+               return get_sdhc_freq(0);
+#endif
        case MXC_DSPI_CLK:
                return get_dspi_freq(0);
        default: