Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fsl_lsch2_speed.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 2d7775e54f494fb34fbd97e7c82e6ff66151dc2a..df4df9aca798ce25edba8e0f6db9a9eb43db5d21 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ * Copyright 2019 NXP.
  */
 
 #include <common.h>
@@ -22,10 +22,12 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#if (defined(CONFIG_FSL_ESDHC) &&\
-       defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
-       defined(CONFIG_SYS_DPAA_FMAN)
-
+/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
+ * mux 2 clock for LS1043A/LS1046A.
+ */
+#if defined(CONFIG_SYS_DPAA_FMAN) || \
+           defined(CONFIG_TARGET_LS1046ARDB) || \
+           defined(CONFIG_TARGET_LS1043ARDB)
        u32 rcw_tmp;
 #endif
        struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -122,32 +124,32 @@ void get_sys_info(struct sys_info *sys_info)
        }
 #endif
 
+#ifdef CONFIG_FSL_ESDHC
 #define HWA_CGA_M2_CLK_SEL     0x00000007
 #define HWA_CGA_M2_CLK_SHIFT   0
-#ifdef CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
        rcw_tmp = in_be32(&gur->rcwsr[15]);
        switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
        case 1:
-               sys_info->freq_sdhc = freq_c_pll[1];
+               sys_info->freq_cga_m2 = freq_c_pll[1];
                break;
+#if defined(CONFIG_TARGET_LS1046ARDB)
        case 2:
-               sys_info->freq_sdhc = freq_c_pll[1] / 2;
+               sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
                break;
+#endif
        case 3:
-               sys_info->freq_sdhc = freq_c_pll[1] / 3;
+               sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
                break;
+#if defined(CONFIG_TARGET_LS1046ARDB)
        case 6:
-               sys_info->freq_sdhc = freq_c_pll[0] / 2;
+               sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
                break;
+#endif
        default:
-               printf("Error: Unknown ESDHC clock select!\n");
+               printf("Error: Unknown peripheral clock select!\n");
                break;
        }
-#else
-       sys_info->freq_sdhc = (sys_info->freq_systembus /
-                               CONFIG_SYS_FSL_PCLK_DIV) /
-                               CONFIG_SYS_FSL_SDHC_CLK_DIV;
 #endif
 #endif
 
@@ -155,7 +157,23 @@ void get_sys_info(struct sys_info *sys_info)
        sys_info->freq_localbus = sys_info->freq_systembus /
                                                CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+       sys_info->freq_qman = (sys_info->freq_systembus /
+                               CONFIG_SYS_FSL_PCLK_DIV) /
+                               CONFIG_SYS_FSL_QMAN_CLK_DIV;
+#endif
+}
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void)
+{
+       struct sys_info sys_info;
+
+       get_sys_info(&sys_info);
+
+       return sys_info.freq_qman;
 }
+#endif
 
 int get_clocks(void)
 {
@@ -167,9 +185,22 @@ int get_clocks(void)
        gd->mem_clk = sys_info.freq_ddrbus;
 
 #ifdef CONFIG_FSL_ESDHC
-       gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
+#if defined(CONFIG_TARGET_LS1046ARDB)
+       gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
+#endif
+#if defined(CONFIG_TARGET_LS1043ARDB)
+       gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+#endif
+#if defined(CONFIG_TARGET_LS1012ARDB)
+       gd->arch.sdhc_clk = sys_info.freq_systembus;
+#endif
+#else
+       gd->arch.sdhc_clk = (sys_info.freq_systembus /
+                       CONFIG_SYS_FSL_PCLK_DIV) /
+                       CONFIG_SYS_FSL_SDHC_CLK_DIV;
+#endif
 #endif
-
        if (gd->cpu_clk != 0)
                return 0;
        else
@@ -235,6 +266,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_i2c_freq(0);
 #if defined(CONFIG_FSL_ESDHC)
        case MXC_ESDHC_CLK:
+       case MXC_ESDHC2_CLK:
                return get_sdhc_freq(0);
 #endif
        case MXC_DSPI_CLK: