CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
+ CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
+ CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
+ CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
};
#define EARLY_PGTABLE_SIZE 0x5000
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
+#ifdef CONFIG_SYS_FSL_DRAM_BASE3
+ { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+ CONFIG_SYS_FSL_DRAM_SIZE3,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#endif
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
CONFIG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
-#ifdef CONFIG_ARCH_LS2080A
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
+#ifdef CONFIG_SYS_FSL_DRAM_BASE3
+ { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+ CONFIG_SYS_FSL_DRAM_SIZE3,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#endif
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
CONFIG_SYS_FSL_BOOTROM_SIZE,
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
strcpy(name, cpu_type_list[i].name);
+#ifdef CONFIG_ARCH_LX2160A
+ if (IS_C_PROCESSOR(svr))
+ strcat(name, "C");
+#endif
if (IS_E_PROCESSOR(svr))
strcat(name, "E");
strcpy(name, "unknown");
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
case CONFIG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#endif
default:
break;
}
icache_enable();
dcache_enable();
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)
{
enum boot_src src = BOOT_SOURCE_RESERVED;
u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
-#if !defined(CONFIG_FSL_LSCH3_2)
+#if !defined(CONFIG_NXP_LSCH3_2)
u32 val;
#endif
debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
#if defined(CONFIG_FSL_LSCH3)
-#if defined(CONFIG_FSL_LSCH3_2)
+#if defined(CONFIG_NXP_LSCH3_2)
switch (rcw_src) {
case RCW_SRC_SDHC1_VAL:
src = BOOT_SOURCE_SD_MMC;
break;
case RCW_SRC_EMMC_VAL:
/* RCW SRC EMMC */
- src = BOOT_SOURCE_SD_MMC2;
+ src = BOOT_SOURCE_SD_MMC;
break;
case RCW_SRC_I2C1_VAL:
/* RCW SRC I2C1 Extended */
}
}
#endif
+
+ if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
+ src = BOOT_SOURCE_QSPI_NOR;
+
debug("%s: src 0x%x\n", __func__, src);
return src;
}
enum boot_src get_boot_src(void)
{
- u32 porsr1;
+ struct pt_regs regs;
+ u32 porsr1 = 0;
#if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
-
- porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#endif
+
+ if (current_el() == 2) {
+ regs.regs[0] = SIP_SVC_RCW;
+
+ smc_call(®s);
+ if (!regs.regs[0])
+ porsr1 = regs.regs[1];
+ }
- porsr1 = in_be32(&gur->porsr1);
+ if (current_el() == 3 || !porsr1) {
+#ifdef CONFIG_FSL_LSCH3
+ porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+ porsr1 = in_be32(&gur->porsr1);
#endif
+ }
+
debug("%s: porsr1 0x%x\n", __func__, porsr1);
return __get_boot_src(porsr1);
printf("Did not wake secondary cores\n");
}
-#ifdef CONFIG_SYS_FSL_HAS_RGMII
- fsl_rgmii_init();
-#endif
-
config_core_prefetch();
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+ /* some dpmacs in armv8a based freescale layerscape SOCs can be
+ * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+ * EC*_PMUX(rgmii) bits in RCW.
+ * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
+ * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
+ * Now if a dpmac is enabled by serdes bits then it takes precedence
+ * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
+ * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
+ * then the dpmac is SGMII and not RGMII.
+ *
+ * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
+ * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
+ * or not? if it is (fsl_serdes_init has already enabled the dpmac),
+ * then don't enable it.
+ */
+ fsl_rgmii_init();
+#endif
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
{
u32 val;
+#ifdef CONFIG_ARCH_LX2160A
+ val = in_le32(rstcr);
+ val |= 0x01;
+ out_le32(rstcr, val);
+#else
/* Raise RESET_REQ_B */
val = scfg_in32(rstcr);
val |= 0x02;
scfg_out32(rstcr, val);
+#endif
}
#ifdef CONFIG_EFI_LOADER
projects / oweals / u-boot.git / blobdiff