armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index be21685eaa8655c70904586b5db3dddd763f7d1a..db7577b6ed35414e0c6d1330bd887c64ccd55b8f 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -251,7 +251,7 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
        { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
          CONFIG_SYS_PCIE4_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -388,7 +388,7 @@ void cpu_name(char *name)
                strcpy(name, "unknown");
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -453,11 +453,13 @@ static void fix_pcie_mmu_map(void)
                                final_map[i].virt = 0x3000000000ULL;
                                final_map[i].size = 0x800000000ULL;
                                break;
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
                        case CONFIG_SYS_PCIE4_PHYS_ADDR:
                                final_map[i].phys = 0x3800000000ULL;
                                final_map[i].virt = 0x3800000000ULL;
                                final_map[i].size = 0x800000000ULL;
                                break;
+#endif
                        default:
                                break;
                        }
@@ -611,7 +613,7 @@ void enable_caches(void)
        icache_enable();
        dcache_enable();
 }
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 #ifdef CONFIG_TFABOOT
 enum boot_src __get_boot_src(u32 porsr1)
@@ -1099,15 +1101,29 @@ int arch_early_init_r(void)
                        printf("Did not wake secondary cores\n");
        }
 
-#ifdef CONFIG_SYS_FSL_HAS_RGMII
-       fsl_rgmii_init();
-#endif
-
        config_core_prefetch();
 
 #ifdef CONFIG_SYS_HAS_SERDES
        fsl_serdes_init();
 #endif
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+       /* some dpmacs in armv8a based freescale layerscape SOCs can be
+        * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+        * EC*_PMUX(rgmii) bits in RCW.
+        * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
+        * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
+        * Now if a dpmac is enabled by serdes bits then it takes precedence
+        * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
+        * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
+        * then the dpmac is SGMII and not RGMII.
+        *
+        * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
+        * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
+        * or not? if it is (fsl_serdes_init has already enabled the dpmac),
+        * then don't enable it.
+        */
+       fsl_rgmii_init();
+#endif
 #ifdef CONFIG_FMAN_ENET
        fman_enet_init();
 #endif