pci: layerscape: add LS2088A series SoC pcie support

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 78e250c1cc991118e21690c0f7eb8440310f4c66..cebbb0fec5ee054c31fdabf33759819de86cafac 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -89,6 +89,49 @@ static inline void early_mmu_setup(void)
        set_sctlr(get_sctlr() | CR_M);
 }
 
+static void fix_pcie_mmu_map(void)
+{
+#ifdef CONFIG_LS2080A
+       unsigned int i;
+       u32 svr, ver;
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+       svr = gur_in32(&gur->svr);
+       ver = SVR_SOC_VER(svr);
+
+       /* Fix PCIE base and size for LS2088A */
+       if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
+           (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
+               for (i = 0; i < ARRAY_SIZE(final_map); i++) {
+                       switch (final_map[i].phys) {
+                       case CONFIG_SYS_PCIE1_PHYS_ADDR:
+                               final_map[i].phys = 0x2000000000ULL;
+                               final_map[i].virt = 0x2000000000ULL;
+                               final_map[i].size = 0x800000000ULL;
+                               break;
+                       case CONFIG_SYS_PCIE2_PHYS_ADDR:
+                               final_map[i].phys = 0x2800000000ULL;
+                               final_map[i].virt = 0x2800000000ULL;
+                               final_map[i].size = 0x800000000ULL;
+                               break;
+                       case CONFIG_SYS_PCIE3_PHYS_ADDR:
+                               final_map[i].phys = 0x3000000000ULL;
+                               final_map[i].virt = 0x3000000000ULL;
+                               final_map[i].size = 0x800000000ULL;
+                               break;
+                       case CONFIG_SYS_PCIE4_PHYS_ADDR:
+                               final_map[i].phys = 0x3800000000ULL;
+                               final_map[i].virt = 0x3800000000ULL;
+                               final_map[i].size = 0x800000000ULL;
+                               break;
+                       default:
+                               break;
+                       }
+               }
+       }
+#endif
+}
+
 /*
  * The final tables look similar to early tables, but different in detail.
  * These tables are in DRAM. Sub tables are added to enable cache for
@@ -103,6 +146,9 @@ static inline void final_mmu_setup(void)
        unsigned int el = current_el();
        int index;
 
+       /* fix the final_map before filling in the block entries */
+       fix_pcie_mmu_map();
+
        mem_map = final_map;
 
        /* Update mapping for DDR to actual size */