Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b32fcb18cbbad8459df6c603417bed1d54..b44389445369c852a6be3b2bcd63c29956221fad 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,11 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <env.h>
 #include <fsl_ddr_sdram.h>
+#include <init.h>
+#include <hang.h>
+#include <vsprintf.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/system.h>
@@ -32,11 +37,12 @@
 #include <fsl_qbman.h>
 
 #ifdef CONFIG_TFABOOT
-#include <environment.h>
+#include <env_internal.h>
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
 #endif
+#include <linux/mii.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -58,6 +64,10 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
        CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
        CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+       CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
+       CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
+       CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
+       CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
        CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
        CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
        CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
@@ -246,17 +256,33 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
          CONFIG_SYS_PCIE3_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#endif
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
        { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
          CONFIG_SYS_PCIE4_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#endif
+#ifdef SYS_PCIE5_PHYS_ADDR
+       { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
+         SYS_PCIE5_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+#endif
+#ifdef SYS_PCIE6_PHYS_ADDR
+       { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
+         SYS_PCIE6_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
 #endif
        { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
          CONFIG_SYS_FSL_WRIOP1_SIZE,
@@ -341,11 +367,13 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
          CONFIG_SYS_PCIE3_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#endif
        { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
          CONFIG_SYS_FSL_DRAM_SIZE3,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) |
@@ -388,7 +416,7 @@ void cpu_name(char *name)
                strcpy(name, "unknown");
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -448,16 +476,20 @@ static void fix_pcie_mmu_map(void)
                                final_map[i].virt = 0x2800000000ULL;
                                final_map[i].size = 0x800000000ULL;
                                break;
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
                        case CONFIG_SYS_PCIE3_PHYS_ADDR:
                                final_map[i].phys = 0x3000000000ULL;
                                final_map[i].virt = 0x3000000000ULL;
                                final_map[i].size = 0x800000000ULL;
                                break;
+#endif
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
                        case CONFIG_SYS_PCIE4_PHYS_ADDR:
                                final_map[i].phys = 0x3800000000ULL;
                                final_map[i].virt = 0x3800000000ULL;
                                final_map[i].size = 0x800000000ULL;
                                break;
+#endif
                        default:
                                break;
                        }
@@ -611,7 +643,7 @@ void enable_caches(void)
        icache_enable();
        dcache_enable();
 }
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 #ifdef CONFIG_TFABOOT
 enum boot_src __get_boot_src(u32 porsr1)
@@ -785,12 +817,8 @@ enum env_location env_get_location(enum env_operation op, int prio)
        if (prio)
                return ENVL_UNKNOWN;
 
-#ifdef CONFIG_CHAIN_OF_TRUST
-       /* Check Boot Mode
-        * If Boot Mode is Secure, return ENVL_NOWHERE
-        */
-       if (fsl_check_boot_mode_secure() == 1)
-               goto done;
+#ifdef CONFIG_ENV_IS_NOWHERE
+       return env_loc;
 #endif
 
        switch (src) {
@@ -820,9 +848,6 @@ enum env_location env_get_location(enum env_operation op, int prio)
                break;
        }
 
-#ifdef CONFIG_CHAIN_OF_TRUST
-done:
-#endif
        return env_loc;
 }
 #endif /* CONFIG_TFABOOT */
@@ -1052,6 +1077,8 @@ static void config_core_prefetch(void)
 
        if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
                buf = buffer;
+       else
+               return;
 
        prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
                                         &arglen, buf);
@@ -1076,6 +1103,12 @@ static void config_core_prefetch(void)
        }
 }
 
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+__weak void set_ecam_icids(void)
+{
+}
+#endif
+
 int arch_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
@@ -1127,6 +1160,9 @@ int arch_early_init_r(void)
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
        setup_qbman_portals();
+#endif
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+       set_ecam_icids();
 #endif
        return 0;
 }
@@ -1137,7 +1173,8 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
        u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
+       defined(CONFIG_ARCH_LS1028A)
        u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
        u32 svr_dev_id;
 #endif
@@ -1156,7 +1193,8 @@ int timer_init(void)
        out_le32(cltbenr, 0xf);
 #endif
 
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
+       defined(CONFIG_ARCH_LS1028A)
        /*
         * In certain Layerscape SoCs, the clock for each core's
         * has an enable bit in the PMU Physical Core Time Base Enable
@@ -1199,7 +1237,7 @@ void __efi_runtime reset_cpu(ulong addr)
 #endif
 }
 
-#ifdef CONFIG_EFI_LOADER
+#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
 
 void __efi_runtime EFIAPI efi_reset_system(
                       enum efi_reset_type reset_type,
@@ -1594,3 +1632,17 @@ __weak int dram_init(void)
 
        return 0;
 }
+
+#ifdef CONFIG_ARCH_MISC_INIT
+__weak int serdes_misc_init(void)
+{
+       return 0;
+}
+
+int arch_misc_init(void)
+{
+       serdes_misc_init();
+
+       return 0;
+}
+#endif