Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 26f4fdacdb829019e6a5832228becc8bcca5027f..b44389445369c852a6be3b2bcd63c29956221fad 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,12 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <env.h>
 #include <fsl_ddr_sdram.h>
+#include <init.h>
+#include <hang.h>
+#include <vsprintf.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/system.h>
@@ -38,6 +42,7 @@
 #include <fsl_validate.h>
 #endif
 #endif
+#include <linux/mii.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -59,6 +64,9 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
        CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
        CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+       CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
+       CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
+       CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
        CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
        CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
        CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
@@ -1069,6 +1077,8 @@ static void config_core_prefetch(void)
 
        if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
                buf = buffer;
+       else
+               return;
 
        prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
                                         &arglen, buf);
@@ -1093,6 +1103,12 @@ static void config_core_prefetch(void)
        }
 }
 
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+__weak void set_ecam_icids(void)
+{
+}
+#endif
+
 int arch_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
@@ -1144,6 +1160,9 @@ int arch_early_init_r(void)
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
        setup_qbman_portals();
+#endif
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+       set_ecam_icids();
 #endif
        return 0;
 }
@@ -1154,7 +1173,8 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
        u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
+       defined(CONFIG_ARCH_LS1028A)
        u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
        u32 svr_dev_id;
 #endif
@@ -1173,7 +1193,8 @@ int timer_init(void)
        out_le32(cltbenr, 0xf);
 #endif
 
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
+       defined(CONFIG_ARCH_LS1028A)
        /*
         * In certain Layerscape SoCs, the clock for each core's
         * has an enable bit in the PMU Physical Core Time Base Enable
@@ -1216,7 +1237,7 @@ void __efi_runtime reset_cpu(ulong addr)
 #endif
 }
 
-#ifdef CONFIG_EFI_LOADER
+#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
 
 void __efi_runtime EFIAPI efi_reset_system(
                       enum efi_reset_type reset_type,
@@ -1611,3 +1632,17 @@ __weak int dram_init(void)
 
        return 0;
 }
+
+#ifdef CONFIG_ARCH_MISC_INIT
+__weak int serdes_misc_init(void)
+{
+       return 0;
+}
+
+int arch_misc_init(void)
+{
+       serdes_misc_init();
+
+       return 0;
+}
+#endif