armv8: sec_firmware: return job ring status as true in TFABOOT

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index e25515ef9bf296d7db9b0eec344bbf18c027a93d..36189f7a92cba50317eec3fb96629379b61efef8 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -693,23 +693,41 @@ enum boot_src __get_boot_src(u32 porsr1)
                }
        }
 #endif
+
+       if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
+               src = BOOT_SOURCE_QSPI_NOR;
+
        debug("%s: src 0x%x\n", __func__, src);
        return src;
 }
 
 enum boot_src get_boot_src(void)
 {
-       u32 porsr1;
+       struct pt_regs regs;
+       u32 porsr1 = 0;
 
 #if defined(CONFIG_FSL_LSCH3)
        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
-
-       porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 #elif defined(CONFIG_FSL_LSCH2)
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#endif
+
+       if (current_el() == 2) {
+               regs.regs[0] = SIP_SVC_RCW;
+
+               smc_call(&regs);
+               if (!regs.regs[0])
+                       porsr1 = regs.regs[1];
+       }
 
-       porsr1 = in_be32(&gur->porsr1);
+       if (current_el() == 3 || !porsr1) {
+#ifdef CONFIG_FSL_LSCH3
+               porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+               porsr1 = in_be32(&gur->porsr1);
 #endif
+       }
+
        debug("%s: porsr1 0x%x\n", __func__, porsr1);
 
        return __get_boot_src(porsr1);
@@ -1229,12 +1247,96 @@ phys_size_t get_effective_memsize(void)
        return ea_size;
 }
 
+#ifdef CONFIG_TFABOOT
+phys_size_t tfa_get_dram_size(void)
+{
+       struct pt_regs regs;
+       phys_size_t dram_size = 0;
+
+       regs.regs[0] = SMC_DRAM_BANK_INFO;
+       regs.regs[1] = -1;
+
+       smc_call(&regs);
+       if (regs.regs[0])
+               return 0;
+
+       dram_size = regs.regs[1];
+       return dram_size;
+}
+
+static int tfa_dram_init_banksize(void)
+{
+       int i = 0, ret = 0;
+       struct pt_regs regs;
+       phys_size_t dram_size = tfa_get_dram_size();
+
+       debug("dram_size %llx\n", dram_size);
+
+       if (!dram_size)
+               return -EINVAL;
+
+       do {
+               regs.regs[0] = SMC_DRAM_BANK_INFO;
+               regs.regs[1] = i;
+
+               smc_call(&regs);
+               if (regs.regs[0]) {
+                       ret = -EINVAL;
+                       break;
+               }
+
+               debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
+                     regs.regs[2]);
+               gd->bd->bi_dram[i].start = regs.regs[1];
+               gd->bd->bi_dram[i].size = regs.regs[2];
+
+               dram_size -= gd->bd->bi_dram[i].size;
+
+               i++;
+       } while (dram_size);
+
+       if (i > 0)
+               ret = 0;
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+       /* Assign memory for MC */
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+       if (gd->bd->bi_dram[2].size >=
+           board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
+               gd->arch.resv_ram = gd->bd->bi_dram[2].start +
+                           gd->bd->bi_dram[2].size -
+                           board_reserve_ram_top(gd->bd->bi_dram[2].size);
+       } else
+#endif
+       {
+               if (gd->bd->bi_dram[1].size >=
+                   board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
+                       gd->arch.resv_ram = gd->bd->bi_dram[1].start +
+                               gd->bd->bi_dram[1].size -
+                               board_reserve_ram_top(gd->bd->bi_dram[1].size);
+               } else if (gd->bd->bi_dram[0].size >
+                          board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
+                       gd->arch.resv_ram = gd->bd->bi_dram[0].start +
+                               gd->bd->bi_dram[0].size -
+                               board_reserve_ram_top(gd->bd->bi_dram[0].size);
+               }
+       }
+#endif /* CONFIG_FSL_MC_ENET */
+
+       return ret;
+}
+#endif
+
 int dram_init_banksize(void)
 {
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
        phys_size_t dp_ddr_size;
 #endif
 
+#ifdef CONFIG_TFABOOT
+       if (!tfa_dram_init_banksize())
+               return 0;
+#endif
        /*
         * gd->ram_size has the total size of DDR memory, less reserved secure
         * memory. The DDR extends from low region to high region(s) presuming