fsl-layerscape: Consolidate registers space defination for CCI-400 bus

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index b24462bede9dec9bfb5c89b7d46fec609331f41a..3e02132537fb1c35a162500bb09afcb03264a958 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -26,6 +26,8 @@ config ARCH_LS1043A
        select SYS_FSL_HAS_DDR4
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
+       imply SCSI
+       imply CMD_PCI
 
 config ARCH_LS1046A
        bool
@@ -36,6 +38,7 @@ config ARCH_LS1046A
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008336
        select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A008850
        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009803
        select SYS_FSL_ERRATUM_A009942
@@ -45,6 +48,7 @@ config ARCH_LS1046A
        select SYS_FSL_SRDS_2
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
+       imply SCSI
 
 config ARCH_LS2080A
        bool
@@ -63,6 +67,8 @@ config ARCH_LS2080A
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_LE
        select SYS_FSL_SRDS_2
+       select FSL_TZASC_1
+       select FSL_TZASC_2
        select SYS_FSL_ERRATUM_A008336
        select SYS_FSL_ERRATUM_A008511
        select SYS_FSL_ERRATUM_A008514
@@ -79,6 +85,7 @@ config ARCH_LS2080A
 
 config FSL_LSCH2
        bool
+       select SYS_FSL_HAS_CCI400
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_BE
@@ -132,6 +139,19 @@ config FSL_LS_PPA
          which is loaded during boot stage, and then remains resident in RAM
          and runs in the TrustZone after boot.
          Say y to enable it.
+
+config SPL_FSL_LS_PPA
+       bool "FSL Layerscape PPA firmware support for SPL build"
+       depends on !ARMV8_PSCI
+       select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       select SEC_FIRMWARE_ARMV8_PSCI
+       select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
+       help
+         The FSL Primary Protected Application (PPA) is a software component
+         which is loaded during boot stage, and then remains resident in RAM
+         and runs in the TrustZone after boot. This is to load PPA during SPL
+         stage instead of the RAM version of U-Boot. Once PPA is initialized,
+         the rest of U-Boot (including RAM version) runs at EL2.
 choice
        prompt "FSL Layerscape PPA firmware loading-media select"
        depends on FSL_LS_PPA
@@ -160,17 +180,42 @@ endchoice
 config SYS_LS_PPA_FW_ADDR
        hex "Address of PPA firmware loading from"
        depends on FSL_LS_PPA
-       default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
-       default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
-       default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
-       default 0x500000 if SYS_LS_PPA_FW_IN_MMC
-       default 0x500000 if SYS_LS_PPA_FW_IN_NAND
+       default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+       default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+       default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+       default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
+       default 0x400000 if SYS_LS_PPA_FW_IN_MMC
+       default 0x400000 if SYS_LS_PPA_FW_IN_NAND
 
        help
          If the PPA firmware locate at XIP flash, such as NOR or
          QSPI flash, this address is a directly memory-mapped.
          If it is in a serial accessed flash, such as NAND and SD
          card, it is a byte offset.
+
+config SYS_LS_PPA_ESBC_ADDR
+       hex "hdr address of PPA firmware loading from"
+       depends on FSL_LS_PPA && CHAIN_OF_TRUST
+       default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+       default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+       default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
+       default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+       default 0x700000 if SYS_LS_PPA_FW_IN_MMC
+       default 0x700000 if SYS_LS_PPA_FW_IN_NAND
+       help
+         If the PPA header firmware locate at XIP flash, such as NOR or
+         QSPI flash, this address is a directly memory-mapped.
+         If it is in a serial accessed flash, such as NAND and SD
+         card, it is a byte offset.
+
+config LS_PPA_ESBC_HDR_SIZE
+       hex "Length of PPA ESBC header"
+       depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
+       default 0x2000
+       help
+         Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
+         NAND to memory to validate PPA image.
+
 endmenu
 
 config SYS_FSL_ERRATUM_A010315
@@ -204,6 +249,15 @@ config QSPI_AHB_INIT
          But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
          bus for those flashes to support the full QSPI flash size.
 
+config SYS_CCI400_OFFSET
+       hex "Offset for CCI400 base"
+       depends on SYS_FSL_HAS_CCI400
+       default 0x3090000 if ARCH_LS1088A
+       default 0x180000 if FSL_LSCH2
+       help
+         Offset for CCI400 base
+         CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
        depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@@ -211,6 +265,9 @@ config SYS_FSL_IFC_BANK_COUNT
        default 4 if ARCH_LS1046A
        default 8 if ARCH_LS2080A
 
+config SYS_FSL_HAS_CCI400
+       bool
+
 config SYS_FSL_HAS_DP_DDR
        bool
 
@@ -223,6 +280,12 @@ config SYS_FSL_SRDS_2
 config SYS_HAS_SERDES
        bool
 
+config FSL_TZASC_1
+       bool
+
+config FSL_TZASC_2
+       bool
+
 endmenu
 
 menu "Layerscape clock tree configuration"
@@ -258,7 +321,7 @@ config SYS_FSL_DSPI_CLK_DIV
        default 2
        help
          This is the divider that is used to derive DSPI clock from Platform
-         PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
+         clock, in another word DSPI_clk = Platform_clk / this_divider.
 
 config SYS_FSL_DUART_CLK_DIV
        int "DUART clock divider"
@@ -343,3 +406,6 @@ config SYS_MC_RSV_MEM_ALIGN
        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.
+
+config SPL_LDSCRIPT
+       default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A