fsl-layerscape: Consolidate registers space defination for CCI-400 bus

[oweals/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5825f9b7264e0fccc6d2d11019e437094d476cfb..3e02132537fb1c35a162500bb09afcb03264a958 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -27,6 +27,7 @@ config ARCH_LS1043A
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        imply SCSI
+       imply CMD_PCI
 
 config ARCH_LS1046A
        bool
@@ -84,6 +85,7 @@ config ARCH_LS2080A
 
 config FSL_LSCH2
        bool
+       select SYS_FSL_HAS_CCI400
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_BE
@@ -247,6 +249,15 @@ config QSPI_AHB_INIT
          But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
          bus for those flashes to support the full QSPI flash size.
 
+config SYS_CCI400_OFFSET
+       hex "Offset for CCI400 base"
+       depends on SYS_FSL_HAS_CCI400
+       default 0x3090000 if ARCH_LS1088A
+       default 0x180000 if FSL_LSCH2
+       help
+         Offset for CCI400 base
+         CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
        depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@@ -254,6 +265,9 @@ config SYS_FSL_IFC_BANK_COUNT
        default 4 if ARCH_LS1046A
        default 8 if ARCH_LS2080A
 
+config SYS_FSL_HAS_CCI400
+       bool
+
 config SYS_FSL_HAS_DP_DDR
        bool
 
@@ -307,7 +321,7 @@ config SYS_FSL_DSPI_CLK_DIV
        default 2
        help
          This is the divider that is used to derive DSPI clock from Platform
-         PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
+         clock, in another word DSPI_clk = Platform_clk / this_divider.
 
 config SYS_FSL_DUART_CLK_DIV
        int "DUART clock divider"
@@ -392,3 +406,6 @@ config SYS_MC_RSV_MEM_ALIGN
        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.
+
+config SPL_LDSCRIPT
+       default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A