/* to activate the MMU we need to set up virtual memory */
static void mmu_setup(void)
{
- int i, j, el;
bd_t *bd = gd->bd;
- u64 *page_table = (u64 *)gd->arch.tlb_addr;
+ u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
+ int el;
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
return (get_sctlr() & CR_C) != 0;
}
-#else /* CONFIG_SYS_DCACHE_OFF */
+u64 *__weak arch_get_page_table(void) {
+ puts("No page table offset defined\n");
-void invalidate_dcache_all(void)
-{
+ return NULL;
}
-void flush_dcache_all(void)
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ enum dcache_option option)
{
+ u64 *page_table = arch_get_page_table();
+ u64 upto, end;
+
+ if (page_table == NULL)
+ return;
+
+ end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
+ MMU_SECTION_SHIFT;
+ start = start >> MMU_SECTION_SHIFT;
+ for (upto = start; upto < end; upto++) {
+ page_table[upto] &= ~PMD_ATTRINDX_MASK;
+ page_table[upto] |= PMD_ATTRINDX(option);
+ }
+ asm volatile("dsb sy");
+ __asm_invalidate_tlb_all();
+ asm volatile("dsb sy");
+ asm volatile("isb");
+ start = start << MMU_SECTION_SHIFT;
+ end = end << MMU_SECTION_SHIFT;
+ flush_dcache_range(start, end);
+ asm volatile("dsb sy");
}
+#else /* CONFIG_SYS_DCACHE_OFF */
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
+void invalidate_dcache_all(void)
{
}
-void flush_dcache_range(unsigned long start, unsigned long stop)
+void flush_dcache_all(void)
{
}
return 0;
}
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ enum dcache_option option)
+{
+}
+
#endif /* CONFIG_SYS_DCACHE_OFF */
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
dcache_enable();
}
-
-/*
- * Flush range from all levels of d-cache/unified-cache
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}