ARM: zynqmp: Add platform specific arch_get_page_table

[oweals/u-boot.git] / arch / arm / cpu / armv8 / cache.S

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 546a83e8f8bb3daeb96260f24c02b32b8f2e0705..d8462365006288d6820415ba66003f2f26fddf3b 100644 (file)
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -9,7 +9,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <asm/macro.h>
 #include <linux/linkage.h>
 
@@ -19,23 +18,22 @@
  * clean and invalidate one level cache.
  *
  * x0: cache level
- * x1~x9: clobbered
+ * x1: 0 flush & invalidate, 1 invalidate only
+ * x2~x9: clobbered
  */
 ENTRY(__asm_flush_dcache_level)
-       lsl     x1, x0, #1
-       msr     csselr_el1, x1          /* select cache level */
+       lsl     x12, x0, #1
+       msr     csselr_el1, x12         /* select cache level */
        isb                             /* sync change of cssidr_el1 */
        mrs     x6, ccsidr_el1          /* read the new cssidr_el1 */
        and     x2, x6, #7              /* x2 <- log2(cache line size)-4 */
        add     x2, x2, #4              /* x2 <- log2(cache line size) */
        mov     x3, #0x3ff
        and     x3, x3, x6, lsr #3      /* x3 <- max number of #ways */
-       add     w4, w3, w3
-       sub     w4, w4, 1               /* round up log2(#ways + 1) */
-       clz     w5, w4                  /* bit position of #ways */
+       clz     w5, w3                  /* bit position of #ways */
        mov     x4, #0x7fff
        and     x4, x4, x6, lsr #13     /* x4 <- max number of #sets */
-       /* x1 <- cache level << 1 */
+       /* x12 <- cache level << 1 */
        /* x2 <- line length offset */
        /* x3 <- number of cache ways - 1 */
        /* x4 <- number of cache sets - 1 */
@@ -45,11 +43,14 @@ loop_set:
        mov     x6, x3                  /* x6 <- working copy of #ways */
 loop_way:
        lsl     x7, x6, x5
-       orr     x9, x1, x7              /* map way and level to cisw value */
+       orr     x9, x12, x7             /* map way and level to cisw value */
        lsl     x7, x4, x2
        orr     x9, x9, x7              /* map set number to cisw value */
-       dc      cisw, x9                /* clean & invalidate by set/way */
-       subs    x6, x6, #1              /* decrement the way */
+       tbz     w1, #0, 1f
+       dc      isw, x9
+       b       2f
+1:     dc      cisw, x9                /* clean & invalidate by set/way */
+2:     subs    x6, x6, #1              /* decrement the way */
        b.ge    loop_way
        subs    x4, x4, #1              /* decrement the set */
        b.ge    loop_set
@@ -58,11 +59,14 @@ loop_way:
 ENDPROC(__asm_flush_dcache_level)
 
 /*
- * void __asm_flush_dcache_all(void)
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 flush & invalidate, 1 invalidate only
  *
  * clean and invalidate all data cache by SET/WAY.
  */
-ENTRY(__asm_flush_dcache_all)
+ENTRY(__asm_dcache_all)
+       mov     x1, x0
        dsb     sy
        mrs     x10, clidr_el1          /* read clidr_el1 */
        lsr     x11, x10, #24
@@ -76,28 +80,44 @@ ENTRY(__asm_flush_dcache_all)
        /* x15 <- return address */
 
 loop_level:
-       lsl     x1, x0, #1
-       add     x1, x1, x0              /* x0 <- tripled cache level */
-       lsr     x1, x10, x1
-       and     x1, x1, #7              /* x1 <- cache type */
-       cmp     x1, #2
+       lsl     x12, x0, #1
+       add     x12, x12, x0            /* x0 <- tripled cache level */
+       lsr     x12, x10, x12
+       and     x12, x12, #7            /* x12 <- cache type */
+       cmp     x12, #2
        b.lt    skip                    /* skip if no cache or icache */
-       bl      __asm_flush_dcache_level
+       bl      __asm_flush_dcache_level        /* x1 = 0 flush, 1 invalidate */
 skip:
        add     x0, x0, #1              /* increment cache level */
        cmp     x11, x0
        b.gt    loop_level
 
        mov     x0, #0
-       msr     csselr_el1, x0          /* resotre csselr_el1 */
+       msr     csselr_el1, x0          /* restore csselr_el1 */
        dsb     sy
        isb
        mov     lr, x15
 
 finished:
        ret
+ENDPROC(__asm_dcache_all)
+
+ENTRY(__asm_flush_dcache_all)
+       mov     x16, lr
+       mov     x0, #0
+       bl      __asm_dcache_all
+       mov     lr, x16
+       ret
 ENDPROC(__asm_flush_dcache_all)
 
+ENTRY(__asm_invalidate_dcache_all)
+       mov     x16, lr
+       mov     x0, #0xffff
+       bl      __asm_dcache_all
+       mov     lr, x16
+       ret
+ENDPROC(__asm_invalidate_dcache_all)
+
 /*
  * void __asm_flush_dcache_range(start, end)
  *
@@ -134,3 +154,9 @@ ENTRY(__asm_invalidate_icache_all)
        isb     sy
        ret
 ENDPROC(__asm_invalidate_icache_all)
+
+ENTRY(__asm_flush_l3_cache)
+       mov     x0, #0                  /* return status as success */
+       ret
+ENDPROC(__asm_flush_l3_cache)
+       .weak   __asm_flush_l3_cache