dsb sy
ret
ENDPROC(__asm_flush_dcache_range)
+/*
+ * void __asm_invalidate_dcache_range(start, end)
+ *
+ * invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+ENTRY(__asm_invalidate_dcache_range)
+ mrs x3, ctr_el0
+ ubfm x3, x3, #16, #19
+ mov x2, #4
+ lsl x2, x2, x3 /* cache line size */
+
+ /* x2 <- minimal cache line size in cache system */
+ sub x3, x2, #1
+ bic x0, x0, x3
+1: dc ivac, x0 /* invalidate data or unified cache */
+ add x0, x0, x2
+ cmp x0, x1
+ b.lo 1b
+ dsb sy
+ ret
+ENDPROC(__asm_invalidate_dcache_range)
/*
* void __asm_invalidate_icache_all(void)
ret
ENDPROC(__asm_invalidate_icache_all)
-ENTRY(__asm_flush_l3_cache)
+ENTRY(__asm_invalidate_l3_dcache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_invalidate_l3_dcache)
+ .weak __asm_invalidate_l3_dcache
+
+ENTRY(__asm_flush_l3_dcache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_flush_l3_dcache)
+ .weak __asm_flush_l3_dcache
+
+ENTRY(__asm_invalidate_l3_icache)
mov x0, #0 /* return status as success */
ret
-ENDPROC(__asm_flush_l3_cache)
- .weak __asm_flush_l3_cache
+ENDPROC(__asm_invalidate_l3_icache)
+ .weak __asm_invalidate_l3_icache
/*
* void __asm_switch_ttbr(ulong new_ttbr)