Merge branch 'sf' of git://git.denx.de/u-boot-blackfin

[oweals/u-boot.git] / arch / arm / cpu / armv7 / tegra2 / board.c

diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index 4530194bf7ecaa76e1457d4bbb03ae90167ba796..349d50e1ac4adbc1b509d0d5a7302d384a42c663 100644 (file)
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -24,12 +24,22 @@
 #include <common.h>
 #include <asm/io.h>
 #include "ap20.h"
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/pmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+       /* UARTs which we can enable */
+       UARTA   = 1 << 0,
+       UARTB   = 1 << 1,
+       UARTD   = 1 << 3,
+       UART_COUNT = 4,
+};
+
 /*
  * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
  * so we are using this value to identify memory size.
@@ -48,35 +58,17 @@ unsigned int query_sdram_size(void)
        case 1:
                return 0x10000000;      /* 256 MB */
        case 2:
+       default:
                return 0x20000000;      /* 512 MB */
        case 3:
-       default:
                return 0x40000000;      /* 1GB */
        }
 }
 
-void s_init(void)
-{
-#ifndef CONFIG_ICACHE_OFF
-       icache_enable();
-#endif
-       invalidate_dcache();
-}
-
 int dram_init(void)
 {
-       unsigned long rs;
-
        /* We do not initialise DRAM here. We just query the size */
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size = gd->ram_size = query_sdram_size();
-
-       /* Now check it dynamically */
-       rs = get_ram_size(CONFIG_SYS_SDRAM_BASE, gd->ram_size);
-       if (rs) {
-               printf("dynamic ram_size = %lu\n", rs);
-               gd->bd->bi_dram[0].size = gd->ram_size = rs;
-       }
+       gd->ram_size = query_sdram_size();
        return 0;
 }
 
@@ -98,6 +90,62 @@ int arch_cpu_init(void)
 {
        /* Fire up the Cortex A9 */
        tegra2_start();
+
+       /* We didn't do this init in start.S, so do it now */
+       cpu_init_cp15();
+
+       /* Initialize essential common plls */
+       clock_early_init();
+
        return 0;
 }
 #endif
+
+/**
+ * Set up the specified uarts
+ *
+ * @param uarts_ids    Mask containing UARTs to init (UARTx)
+ */
+static void setup_uarts(int uart_ids)
+{
+       static enum periph_id id_for_uart[] = {
+               PERIPH_ID_UART1,
+               PERIPH_ID_UART2,
+               PERIPH_ID_UART3,
+               PERIPH_ID_UART4,
+       };
+       size_t i;
+
+       for (i = 0; i < UART_COUNT; i++) {
+               if (uart_ids & (1 << i)) {
+                       enum periph_id id = id_for_uart[i];
+
+                       funcmux_select(id, FUNCMUX_DEFAULT);
+                       clock_ll_start_uart(id);
+               }
+       }
+}
+
+void board_init_uart_f(void)
+{
+       int uart_ids = 0;       /* bit mask of which UART ids to enable */
+
+#ifdef CONFIG_TEGRA2_ENABLE_UARTA
+       uart_ids |= UARTA;
+#endif
+#ifdef CONFIG_TEGRA2_ENABLE_UARTB
+       uart_ids |= UARTB;
+#endif
+#ifdef CONFIG_TEGRA2_ENABLE_UARTD
+       uart_ids |= UARTD;
+#endif
+       setup_uarts(uart_ids);
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif