sunxi: Enable non-secure access to RTC on sun6i (A31s)

[oweals/u-boot.git] / arch / arm / cpu / armv7 / sunxi / rsb.c

diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index b00befb30119bf547a56270a106359f5bf61c81c..6fd11f1529833f3e484a4b3d6bd488d28c7981b0 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -21,15 +21,15 @@ static int rsb_set_device_mode(void);
 static void rsb_cfg_io(void)
 {
 #ifdef CONFIG_MACH_SUN8I
-       sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
-       sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
+       sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+       sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
        sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
        sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
        sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
        sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
 #elif defined CONFIG_MACH_SUN9I
-       sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
-       sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
+       sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+       sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
        sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
        sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
        sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
@@ -60,11 +60,12 @@ int rsb_init(void)
        struct sunxi_rsb_reg * const rsb =
                (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 
-       rsb_cfg_io();
-
        /* Enable RSB and PIO clk, and de-assert their resets */
        prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
 
+       /* Setup external pins */
+       rsb_cfg_io();
+
        writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
        rsb_set_clk();