sunxi: Enable non-secure access to RTC on sun6i (A31s)

[oweals/u-boot.git] / arch / arm / cpu / armv7 / sunxi / psci_sun6i.S

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 251680440fc1a51ef264c2f452bc5c0329253983..4ff46e4fc0b9c1a9020d605ac6f7dbcd407b6439 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -18,6 +18,8 @@
  */
 
 #include <config.h>
+
+#include <asm/arch-armv7/generictimer.h>
 #include <asm/gic.h>
 #include <asm/macro.h>
 #include <asm/psci.h>
@@ -43,26 +45,6 @@
 #define        GICD_BASE               0x1c81000
 #define        GICC_BASE               0x1c82000
 
-.macro timer_wait      reg, ticks
-       @ Program CNTP_TVAL
-       movw    \reg, #(\ticks & 0xffff)
-       movt    \reg, #(\ticks >> 16)
-       mcr     p15, 0, \reg, c14, c2, 0
-       isb
-       @ Enable physical timer, mask interrupt
-       mov     \reg, #3
-       mcr     p15, 0, \reg, c14, c2, 1
-       @ Poll physical timer until ISTATUS is on
-1:     isb
-       mrc     p15, 0, \reg, c14, c2, 1
-       ands    \reg, \reg, #4
-       bne     1b
-       @ Disable timer
-       mov     \reg, #0
-       mcr     p15, 0, \reg, c14, c2, 1
-       isb
-.endm
-
 .globl psci_fiq_enter
 psci_fiq_enter:
        push    {r0-r12}
@@ -124,11 +106,13 @@ psci_fiq_enter:
        str     r10, [r8, #0x100]
        timer_wait r10, ONE_MS
 
+#ifdef CONFIG_MACH_SUN6I
        @ Activate power clamp
        lsl     r12, r9, #2             @ x4
        add     r12, r12, r8
        mov     r10, #0xff
        str     r10, [r12, #0x140]
+#endif
 
        movw    r8, #(SUN6I_CPUCFG_BASE & 0xffff)
        movt    r8, #(SUN6I_CPUCFG_BASE >> 16)
@@ -186,6 +170,7 @@ psci_cpu_on:
        movw    r0, #(SUNXI_PRCM_BASE & 0xffff)
        movt    r0, #(SUNXI_PRCM_BASE >> 16)
 
+#ifdef CONFIG_MACH_SUN6I
        @ Release power clamp
        lsl     r5, r1, #2      @ 1 register per CPU
        add     r5, r5, r0      @ PRCM
@@ -194,6 +179,7 @@ psci_cpu_on:
 1:     lsrs    r6, r6, #1
        str     r6, [r5, #0x140] @ CPUx_PWR_CLAMP
        bne     1b
+#endif
 
        timer_wait r6, TEN_MS