Merge branch 'master' of http://git.denx.de/u-boot-sunxi

[oweals/u-boot.git] / arch / arm / cpu / armv7 / sunxi / dram_sun8i_a23.c

diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c
index 3d7964d1af72b71359102bd541052d27962224b7..c53671a0e9b835b9a528d50fe82c19a2b6afd655 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c
@@ -31,7 +31,8 @@ static const struct dram_para dram_para = {
        .clock = CONFIG_DRAM_CLK,
        .type = 3,
        .zq = CONFIG_DRAM_ZQ,
-       .odt_en = 1,
+       .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
+       .odt_correction = CONFIG_DRAM_ODT_CORRECTION,
        .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
        .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
        .mr0 = 6736,
@@ -97,7 +98,6 @@ static void mctl_init(u32 *bus_width)
                (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
        struct sunxi_mctl_phy_reg * const mctl_phy =
                (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
-       int correction;
 
        if (dram_para.tpr13 & 0x20)
                writel(0x40b, &mctl_phy->dcr);
@@ -138,7 +138,7 @@ static void mctl_init(u32 *bus_width)
 
        writel(0x01000081, &mctl_phy->dtcr);
 
-       if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) {
+       if (dram_para.clock <= 240 || !dram_para.odt_en) {
                clrbits_le32(&mctl_phy->dx0gcr, 0x600);
                clrbits_le32(&mctl_phy->dx1gcr, 0x600);
        }
@@ -251,13 +251,11 @@ static void mctl_init(u32 *bus_width)
        } else
                *bus_width = 16;
 
-       correction = (dram_para.odt_en >> 8) & 0xff;
-       if (correction) {
-               if (dram_para.odt_en & 0x80000000)
-                       correction = -correction;
-
-               mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction);
-               mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction);
+       if (dram_para.odt_correction) {
+               mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1,
+                                         dram_para.odt_correction);
+               mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1,
+                                         dram_para.odt_correction);
        }
 
        mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);