Merge branch 'master' of http://git.denx.de/u-boot-sunxi

[oweals/u-boot.git] / arch / arm / cpu / armv7 / sunxi / clock_sun6i.c

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 8e949c6901d2e1e6299825b1c6b4f9c17e2fc01e..3ab3b31867807ced4d593bffdb7021211e9e7bf5 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -45,10 +45,10 @@ void clock_init_safe(void)
 
 void clock_init_uart(void)
 {
+#if CONFIG_CONS_INDEX < 5
        struct sunxi_ccm_reg *const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-#if CONFIG_CONS_INDEX < 5
        /* uart clock source is apb2 */
        writel(APB2_CLK_SRC_OSC24M|
               APB2_CLK_RATE_N_1|
@@ -68,9 +68,6 @@ void clock_init_uart(void)
        /* enable R_PIO and R_UART clocks, and de-assert resets */
        prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
 #endif
-
-       /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
-       writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 }
 
 int clock_twi_onoff(int port, int state)
@@ -97,6 +94,7 @@ void clock_set_pll1(unsigned int clk)
 {
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       const int p = 0;
        int k = 1;
        int m = 1;
 
@@ -113,8 +111,11 @@ void clock_set_pll1(unsigned int clk)
               CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
               &ccm->cpu_axi_cfg);
 
-       /* PLL1 rate = 24000000 * n * k / m */
-       writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
+       /*
+        * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
+        * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
+        */
+       writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
               CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
               CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
        sdelay(200);
@@ -144,21 +145,102 @@ void clock_set_pll3(unsigned int clk)
               &ccm->pll3_cfg);
 }
 
-void clock_set_pll5(unsigned int clk)
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 {
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-       const int k = 2;
-       const int m = 1;
+       const int max_n = 32;
+       int k = 1, m = 2;
+
+       if (sigma_delta_enable)
+               writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
 
        /* PLL5 rate = 24000000 * n * k / m */
-       writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+       if (clk > 24000000 * k * max_n / m) {
+               m = 1;
+               if (clk > 24000000 * k * max_n / m)
+                       k = 2;
+       }
+       writel(CCM_PLL5_CTRL_EN |
+              (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
+              CCM_PLL5_CTRL_UPD |
               CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
               CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
 
        udelay(5500);
 }
 
+#ifdef CONFIG_MACH_SUN6I
+void clock_set_mipi_pll(unsigned int clk)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       unsigned int k, m, n, value, diff;
+       unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
+       unsigned int src = clock_get_pll3();
+
+       /* All calculations are in KHz to avoid overflows */
+       clk /= 1000;
+       src /= 1000;
+
+       /* Pick the closest lower clock */
+       for (k = 1; k <= 4; k++) {
+               for (m = 1; m <= 16; m++) {
+                       for (n = 1; n <= 16; n++) {
+                               value = src * n * k / m;
+                               if (value > clk)
+                                       continue;
+
+                               diff = clk - value;
+                               if (diff < best_diff) {
+                                       best_diff = diff;
+                                       best_k = k;
+                                       best_m = m;
+                                       best_n = n;
+                               }
+                               if (diff == 0)
+                                       goto done;
+                       }
+               }
+       }
+
+done:
+       writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
+              CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
+              CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
+}
+#endif
+
+#ifdef CONFIG_MACH_SUN8I_A33
+void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       if (sigma_delta_enable)
+               writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
+
+       writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
+              (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
+              CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
+
+       while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
+               ;
+}
+#endif
+
+unsigned int clock_get_pll3(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       uint32_t rval = readl(&ccm->pll3_cfg);
+       int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
+       int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
+
+       /* Multiply by 1000 after dividing by m to avoid integer overflows */
+       return (24000 * n / m) * 1000;
+}
+
 unsigned int clock_get_pll6(void)
 {
        struct sunxi_ccm_reg *const ccm =
@@ -169,6 +251,20 @@ unsigned int clock_get_pll6(void)
        return 24000000 * n * k / 2;
 }
 
+unsigned int clock_get_mipi_pll(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       uint32_t rval = readl(&ccm->mipi_pll_cfg);
+       unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
+       unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
+       unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
+       unsigned int src = clock_get_pll3();
+
+       /* Multiply by 1000 after dividing by m to avoid integer overflows */
+       return ((src / 1000) * n * k / m) * 1000;
+}
+
 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 {
        int pll = clock_get_pll6() * 2;