#include <asm-offsets.h>
#include <config.h>
-#include <version.h>
#include <asm/system.h>
#include <linux/linkage.h>
+#include <asm/armv7.h>
/*************************************************************************
*
* Startup Code (reset vector)
*
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
+ * Do important init only if we don't start from memory!
+ * Setup memory and board specific bits prior to relocation.
+ * Relocate armboot to ram. Setup stack.
*
*************************************************************************/
.globl reset
.globl save_boot_params_ret
+#ifdef CONFIG_ARMV7_LPAE
+ .global switch_to_hypervisor_ret
+#endif
reset:
/* Allow the board to save important registers */
b save_boot_params
save_boot_params_ret:
+#ifdef CONFIG_ARMV7_LPAE
+/*
+ * check for Hypervisor support
+ */
+ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
+ and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
+ cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
+ beq switch_to_hypervisor
+switch_to_hypervisor_ret:
+#endif
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_cp15
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
bl cpu_init_crit
+#endif
#endif
bl _main
ENDPROC(save_boot_params)
.weak save_boot_params
+#ifdef CONFIG_ARMV7_LPAE
+ENTRY(switch_to_hypervisor)
+ b switch_to_hypervisor_ret
+ENDPROC(switch_to_hypervisor)
+ .weak switch_to_hypervisor
+#endif
+
/*************************************************************************
*
* cpu_init_cp15
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
- mov pc, lr @ back to my caller
+ mov r5, lr @ Store my Caller
+ mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
+ mov r3, r1, lsr #20 @ get variant field
+ and r3, r3, #0xf @ r3 has CPU variant
+ and r4, r1, #0xf @ r4 has CPU revision
+ mov r2, r3, lsl #4 @ shift variant field for combined value
+ orr r2, r4, r2 @ r2 has combined CPU variant + revision
+
+#ifdef CONFIG_ARM_ERRATA_798870
+ cmp r2, #0x30 @ Applies to lower than R3p0
+ bge skip_errata_798870 @ skip if not affected rev
+ cmp r2, #0x20 @ Applies to including and above R2p0
+ blt skip_errata_798870 @ skip if not affected rev
+
+ mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
+ orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_l2aux_ctrl
+ isb @ Recommended ISB after l2actlr update
+ pop {r1-r5} @ Restore the cpu info - fall through
+skip_errata_798870:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_801819
+ cmp r2, #0x24 @ Applies to lt including R2p4
+ bgt skip_errata_801819 @ skip if not affected rev
+ cmp r2, #0x20 @ Applies to including and above R2p0
+ blt skip_errata_801819 @ skip if not affected rev
+ mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
+ and r0, r0, #1 << 3 @ check REVIDR[3]
+ cmp r0, #1 << 3
+ beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
+
+ mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
+ orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
+ @ lines allocate in the L1 or L2 cache.
+ orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
+ @ lines allocate in the L1 cache.
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+skip_errata_801819:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_454179
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_454179
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_454179:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_430973
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_430973
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x1 << 6) @ Set IBE bit
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_430973:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_621766
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_621766
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_621766:
+#endif
+
+ mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
/*************************************************************************
*
* CPU_init_critical registers