replace CONFIG_PRELOADER with CONFIG_SPL_BUILD

[oweals/u-boot.git] / arch / arm / cpu / armv7 / start.S

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index cb4f92f3a9da786c4873b919e13af6a16ea5f9a9..5c87e9c333574bdfb4098ade35715d77f646043a 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,18 @@ _end_vect:
 _TEXT_BASE:
        .word   CONFIG_SYS_TEXT_BASE
 
+#ifdef CONFIG_TEGRA2
+/*
+ * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
+ * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
+ * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
+ * to pick up its reset vector, which points here.
+ */
+.globl _armboot_start
+_armboot_start:
+       .word _start
+#endif
+
 /*
  * These are defined in the board-specific linker script.
  */
@@ -79,6 +91,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+       .word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
        .word _end - _start
 
 #ifdef CONFIG_USE_IRQ
@@ -111,7 +127,7 @@ reset:
        orr     r0, r0, #0xd3
        msr     cpsr,r0
 
-#if (CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
        /* Copy vectors to mask ROM indirect addr */
        adr     r0, _start              @ r0 <- current position of code
        add     r0, r0, #4              @ skip reset vector
@@ -166,7 +182,7 @@ stack_setup:
        mov     sp, r4
 
        adr     r0, _start
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
        cmp     r0, r6
        beq     clear_bss               /* skip relocation */
 #endif
@@ -180,7 +196,7 @@ copy_loop:
        cmp     r0, r2                  /* until source end address [r2]    */
        blo     copy_loop
 
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
        /*
         * fix .rel.dyn relocations
         */
@@ -232,13 +248,21 @@ clbss_l:str       r2, [r0]                /* clear loop...                    */
        add     r0, r0, #4
        cmp     r0, r1
        bne     clbss_l
-#endif /* #ifndef CONFIG_PRELOADER */
+#endif /* #ifndef CONFIG_SPL_BUILD */
 
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 jump_2_ram:
+/*
+ * If I-cache is enabled invalidate it
+ */
+#ifndef CONFIG_SYS_ICACHE_OFF
+       mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
+       mcr     p15, 0, r0, c7, c10, 4  @ DSB
+       mcr     p15, 0, r0, c7, c5, 4   @ ISB
+#endif
        ldr     r0, _board_init_r_ofs
        adr     r1, _start
        add     lr, r0, r1
@@ -259,6 +283,7 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*************************************************************************
  *
  * CPU_init_critical registers
@@ -274,6 +299,9 @@ cpu_init_crit:
        mov     r0, #0                  @ set up for MCR
        mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
        mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
+       mcr     p15, 0, r0, c7, c5, 6   @ invalidate BP array
+       mcr     p15, 0, r0, c7, c10, 4  @ DSB
+       mcr     p15, 0, r0, c7, c5, 4   @ ISB
 
        /*
         * disable MMU stuff and caches
@@ -282,7 +310,12 @@ cpu_init_crit:
        bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
        bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
        orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
-       orr     r0, r0, #0x00000800     @ set bit 12 (Z---) BTB
+       orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
+#ifdef CONFIG_SYS_ICACHE_OFF
+       bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
+#else
+       orr     r0, r0, #0x00001000     @ set bit 12 (I) I-cache
+#endif
        mcr     p15, 0, r0, c1, c0, 0
 
        /*
@@ -295,6 +328,7 @@ cpu_init_crit:
        bl      lowlevel_init           @ go setup pll,mux,memory
        mov     lr, ip                  @ restore link
        mov     pc, lr                  @ back to my caller
+#endif
 /*
  *************************************************************************
  *