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ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2
[oweals/u-boot.git] / arch / arm / cpu / armv7 / omap5 / hw_data.c
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 95f16866e6cbd9e043dcdf969a937e648bbd13a8..e0ee23f3d1fa3f8d5801ba0eb7a3896e7373c08b 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -320,6 +320,7 @@ struct pmic_data palmas = {
        .pmic_write     = omap_vc_bypass_send_value,
 };
 
+/* The TPS659038 and TPS65917 are software-compatible, use common struct */
 struct pmic_data tps659038 = {
        .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
        .step = 10000, /* 10 mV represented in uV */
@@ -394,34 +395,38 @@ struct vcores_data dra752_volts = {
 };
 
 struct vcores_data dra722_volts = {
-       .mpu.value      = 1000,
+       .mpu.value      = VDD_MPU_DRA72x,
        .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
-       .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .mpu.addr       = 0x23,
+       .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
        .mpu.pmic       = &tps659038,
 
-       .eve.value      = 1000,
-       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
-       .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .eve.addr       = 0x2f,
-       .eve.pmic       = &tps659038,
+       .core.value     = VDD_CORE_DRA72x,
+       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .core.addr      = TPS65917_REG_ADDR_SMPS2,
+       .core.pmic      = &tps659038,
 
-       .gpu.value      = 1000,
+       /*
+        * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+        * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+        */
+       .gpu.value      = VDD_GPU_DRA72x,
        .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
-       .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .gpu.addr       = 0x2f,
+       .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
        .gpu.pmic       = &tps659038,
 
-       .core.value     = 1000,
-       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
-       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .core.addr      = 0x27,
-       .core.pmic      = &tps659038,
+       .eve.value      = VDD_EVE_DRA72x,
+       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+       .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .eve.addr       = TPS65917_REG_ADDR_SMPS3,
+       .eve.pmic       = &tps659038,
 
-       .iva.value      = 1000,
+       .iva.value      = VDD_IVA_DRA72x,
        .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
-       .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .iva.addr       = 0x2f,
+       .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .iva.addr       = TPS65917_REG_ADDR_SMPS3,
        .iva.pmic       = &tps659038,
 };
 
@@ -455,6 +460,13 @@ void enable_basic_clocks(void)
                (*prcm)->cm_l4per_gpio6_clkctrl,
                (*prcm)->cm_l4per_gpio7_clkctrl,
                (*prcm)->cm_l4per_gpio8_clkctrl,
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
+               (*prcm)->cm_l3init_ocp2scp1_clkctrl,
+               (*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+#endif
+#endif
                0
        };
 
@@ -486,6 +498,29 @@ void enable_basic_clocks(void)
        setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_MASK);
 
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
+       /* Enable 960 MHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+                    OPTFCLKEN_REFCLK960M);
+
+       /* Enable 32 KHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+                    USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+       /* Enable 960 MHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+                    OPTFCLKEN_REFCLK960M);
+
+       /* Enable 32 KHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+                    USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+       /* Enable 60 MHz clock for USB2PHY2 */
+       setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
+                    L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
+#endif
+#endif
+
        /* Set the correct clock dividers for mmc */
        setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
@@ -515,6 +550,9 @@ void enable_basic_clocks(void)
 void enable_basic_uboot_clocks(void)
 {
        u32 const clk_domains_essential[] = {
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_ipu_clkstctrl,
+#endif
                0
        };
 
@@ -528,7 +566,11 @@ void enable_basic_uboot_clocks(void)
                (*prcm)->cm_l4per_i2c2_clkctrl,
                (*prcm)->cm_l4per_i2c3_clkctrl,
                (*prcm)->cm_l4per_i2c4_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_ipu_i2c5_clkctrl,
+#else
                (*prcm)->cm_l4per_i2c5_clkctrl,
+#endif
                (*prcm)->cm_l3init_hsusbhost_clkctrl,
                (*prcm)->cm_l3init_fsusb_clkctrl,
                0
@@ -539,6 +581,47 @@ void enable_basic_uboot_clocks(void)
                         1);
 }
 
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+       u32 const clk_domains_edma3[] = {
+               0
+       };
+
+       u32 const clk_modules_hw_auto_edma3[] = {
+               (*prcm)->cm_l3main1_tptc1_clkctrl,
+               (*prcm)->cm_l3main1_tptc2_clkctrl,
+               0
+       };
+
+       u32 const clk_modules_explicit_en_edma3[] = {
+               0
+       };
+
+       do_enable_clocks(clk_domains_edma3,
+                        clk_modules_hw_auto_edma3,
+                        clk_modules_explicit_en_edma3,
+                        1);
+}
+
+void disable_edma3_clocks(void)
+{
+       u32 const clk_domains_edma3[] = {
+               0
+       };
+
+       u32 const clk_modules_disable_edma3[] = {
+               (*prcm)->cm_l3main1_tptc1_clkctrl,
+               (*prcm)->cm_l3main1_tptc2_clkctrl,
+               0
+       };
+
+       do_disable_clocks(clk_domains_edma3,
+                         clk_modules_disable_edma3,
+                         1);
+}
+#endif
+
 const struct ctrl_ioregs ioregs_omap5430 = {
        .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
        .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
@@ -573,8 +656,8 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
        .ctrl_ddrch = 0x40404040,
        .ctrl_lpddr2ch = 0x40404040,
        .ctrl_ddr3ch = 0x80808080,
-       .ctrl_ddrio_0 = 0xA2084210,
-       .ctrl_ddrio_1 = 0x84210840,
+       .ctrl_ddrio_0 = 0x00094A40,
+       .ctrl_ddrio_1 = 0x04A52000,
        .ctrl_ddrio_2 = 0x84210000,
        .ctrl_emif_sdram_config_ext = 0x0001C1A7,
        .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
@@ -585,8 +668,8 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
        .ctrl_ddrch = 0x40404040,
        .ctrl_lpddr2ch = 0x40404040,
        .ctrl_ddr3ch = 0x60606080,
-       .ctrl_ddrio_0 = 0xA2084210,
-       .ctrl_ddrio_1 = 0x84210840,
+       .ctrl_ddrio_0 = 0x00094A40,
+       .ctrl_ddrio_1 = 0x04A52000,
        .ctrl_ddrio_2 = 0x84210000,
        .ctrl_emif_sdram_config_ext = 0x0001C1A7,
        .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
@@ -617,6 +700,7 @@ void __weak hw_data_init(void)
 
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA752_ES2_0:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra7xx_dplls;
        *omap_vcores = &dra752_volts;
@@ -652,6 +736,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA752_ES2_0:
                *regs = &ioregs_dra7xx_es1;
                break;
        case DRA722_ES1_0:
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