* Copyright (C) 2004-2010
* Texas Instruments Incorporated - http://www.ti.com/
*
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
* Author :
* Vaibhav Hiremath <hvaibhav@ti.com>
*
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
+DECLARE_GLOBAL_DATA_PTR;
extern omap3_sysinfo sysinfo;
static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
return 0;
offset = readl(&sdrc_base->cs_cfg);
- offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+ offset = (offset & 15) << 27 | (offset & 0x30) << 17;
return offset;
}
/*
* do_sdrc_init -
* - Initialize the SDRAM for use.
- * - Sets up SDRC timings for CS0
* - code called once in C-Stack only context for CS0 and a possible 2nd
* time depending on memory configuration from stack+global context
*/
void do_sdrc_init(u32 cs, u32 early)
{
- struct sdrc_actim *sdrc_actim_base;
-
- if (cs)
- sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
- else
- sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+ struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
if (early) {
/* reset sdrc controller */
sdelay(0x20000);
}
- writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
- RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
- DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
- writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
- writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
- writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
+/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
+ * to prevent this to be build in non-SPL build */
+#ifdef CONFIG_SPL_BUILD
+ /* If we use a SPL there is no x-loader nor config header so we have
+ * to do the job ourselfs
+ */
+ if (cs == CS0) {
+ sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+ /* General SDRC config */
+ writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
+ writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
+
+ /* AC timings */
+ writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+ writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
- writel(CMD_NOP, &sdrc_base->cs[cs].manual);
- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ /* Initialize */
+ writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+ writel(V_MR, &sdrc_base->cs[cs].mr);
+ }
+#endif
/*
- * CAS latency 3, Write Burst = Read Burst, Serial Mode,
- * Burst length = 4
+ * SDRC timings are set up by x-load or config header
+ * We don't need to redo them here.
+ * Older x-loads configure only CS0
+ * configure CS1 to handle this ommission
*/
- writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+ if (cs == CS1) {
+ sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+ sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+ writel(readl(&sdrc_base->cs[CS0].mcfg),
+ &sdrc_base->cs[CS1].mcfg);
+ writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
+ &sdrc_base->cs[CS1].rfr_ctrl);
+ writel(readl(&sdrc_actim_base0->ctrla),
+ &sdrc_actim_base1->ctrla);
+ writel(readl(&sdrc_actim_base0->ctrlb),
+ &sdrc_actim_base1->ctrlb);
+
+ writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(readl(&sdrc_base->cs[CS0].mr),
+ &sdrc_base->cs[CS1].mr);
+ }
+ /*
+ * Test ram in this bank
+ * Disable if bad or not present
+ */
if (!mem_ok(cs))
writel(0, &sdrc_base->cs[cs].mcfg);
}
*/
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
size1 = get_sdr_cs_size(CS1);
}
+ gd->ram_size = size0 + size1;
+
+ return 0;
+}
+
+void dram_init_banksize (void)
+{
+ unsigned int size0 = 0, size1 = 0;
+
+ size0 = get_sdr_cs_size(CS0);
+ size1 = get_sdr_cs_size(CS1);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
-
- return 0;
}
/*