Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[oweals/u-boot.git] / arch / arm / cpu / armv7 / omap3 / sdrc.c

diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index a4979ce61d04762a94cc17e0635b998f559fbbc0..0dd1955431dc89787a9c70289e328fae483881ce 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -8,6 +8,9 @@
  * Copyright (C) 2004-2010
  * Texas Instruments Incorporated - http://www.ti.com/
  *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
  * Author :
  *     Vaibhav Hiremath <hvaibhav@ti.com>
  *
@@ -37,6 +40,7 @@
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 extern omap3_sysinfo sysinfo;
 
 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
@@ -132,13 +136,40 @@ void do_sdrc_init(u32 cs, u32 early)
                sdelay(0x20000);
        }
 
+/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
+ * to prevent this to be build in non-SPL build */
+#ifdef CONFIG_SPL_BUILD
+       /* If we use a SPL there is no x-loader nor config header so we have
+        * to do the job ourselfs
+        */
+       if (cs == CS0) {
+               sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+               /* General SDRC config */
+               writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
+               writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
+
+               /* AC timings */
+               writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+               writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+
+               /* Initialize */
+               writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+               writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+               writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+               writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+               writel(V_MR, &sdrc_base->cs[cs].mr);
+       }
+#endif
+
        /*
         * SDRC timings are set up by x-load or config header
         * We don't need to redo them here.
         * Older x-loads configure only CS0
         * configure CS1 to handle this ommission
         */
-       if (cs) {
+       if (cs == CS1) {
                sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
                sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
                writel(readl(&sdrc_base->cs[CS0].mcfg),
@@ -172,7 +203,6 @@ void do_sdrc_init(u32 cs, u32 early)
  */
 int dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int size0 = 0, size1 = 0;
 
        size0 = get_sdr_cs_size(CS0);
@@ -194,7 +224,6 @@ int dram_init(void)
 
 void dram_init_banksize (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int size0 = 0, size1 = 0;
 
        size0 = get_sdr_cs_size(CS0);