OMAP3 SPL: Add identify_nand_chip function

[oweals/u-boot.git] / arch / arm / cpu / armv7 / omap3 / clock.c

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 3d38d08ccbfee81062c442a65deb1dd3af0c1f5d..e0d65c7a4abca53006f58ca679fa6e657f82579e 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -399,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
                /* L3 */
                sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
                /* GFX */
-               sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
+               sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV_36X);
                /* RESET MGR */
                sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
                /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
@@ -579,6 +579,7 @@ void prcm_init(void)
 
                dpll3_init_36xx(0, clk_index);
                dpll4_init_36xx(0, clk_index);
+               dpll5_init_34xx(0, clk_index);
                iva_init_36xx(0, clk_index);
                mpu_init_36xx(0, clk_index);
 
@@ -607,7 +608,9 @@ void prcm_init(void)
                dpll3_init_34xx(sil_index, clk_index);
                dpll4_init_34xx(sil_index, clk_index);
                dpll5_init_34xx(sil_index, clk_index);
-               iva_init_34xx(sil_index, clk_index);
+               if (get_cpu_family() != CPU_AM35XX)
+                       iva_init_34xx(sil_index, clk_index);
+
                mpu_init_34xx(sil_index, clk_index);
 
                /* Lock MPU DPLL to set frequency */
@@ -674,7 +677,9 @@ void per_clocks_enable(void)
        /* Enable the ICLK for 32K Sync Timer as its used in udelay */
        sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
 
-       sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
+       if (get_cpu_family() != CPU_AM35XX)
+               sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
+
        sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
        sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
        sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
@@ -682,8 +687,10 @@ void per_clocks_enable(void)
        sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
        sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
        sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
-       sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
-       sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+       if (get_cpu_family() != CPU_AM35XX) {
+               sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
+               sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+       }
        sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
        sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);