Merge branch 'master' of git://git.denx.de/u-boot-x86
[oweals/u-boot.git] / arch / arm / cpu / armv7 / omap3 / board.c
index a9fdb4f8ed918f22516f0ab3e064052d6f011c08..637ab7b6bf07334a1b5e5c8afc45ae1c38da0a18 100644 (file)
@@ -40,6 +40,7 @@
 #include <asm/armv7.h>
 #include <asm/arch/gpio.h>
 #include <asm/omap_common.h>
+#include <i2c.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
@@ -89,18 +90,12 @@ u32 omap_boot_device(void)
        return omap3_boot_device;
 }
 
-#endif /* CONFIG_SPL_BUILD */
-
-
-/******************************************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- *****************************************************************************/
-static inline void delay(unsigned long loops)
+void spl_board_init(void)
 {
-       __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-                         "bne 1b":"=r" (loops):"0"(loops));
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 }
+#endif /* CONFIG_SPL_BUILD */
+
 
 /******************************************************************************
  * Routine: secure_unlock
@@ -149,7 +144,7 @@ void secureworld_exit()
 {
        unsigned long i;
 
-       /* configrue non-secure access control register */
+       /* configure non-secure access control register */
        __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
        /* enabling co-processor CP10 and CP11 accesses in NS world */
        __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
@@ -227,14 +222,20 @@ void s_init(void)
 #endif
 
        set_muxconf_regs();
-       delay(100);
+       sdelay(100);
 
        prcm_init();
 
        per_clocks_enable();
 
+#ifdef CONFIG_USB_EHCI_OMAP
+       ehci_clocks_enable();
+#endif
+
 #ifdef CONFIG_SPL_BUILD
        preloader_console_init();
+
+       timer_init();
 #endif
 
        if (!in_sdram)
@@ -392,7 +393,7 @@ static void omap3_setup_aux_cr(void)
 {
        /* Workaround for Cortex-A8 errata: #454179 #430973
         *      Set "IBE" bit
-        *      Set "Disable Brach Size Mispredicts" bit
+        *      Set "Disable Branch Size Mispredicts" bit
         * Workaround for erratum #621766
         *      Enable L1NEON bit
         * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0