{
unsigned long i;
- /* configrue non-secure access control register */
+ /* configure non-secure access control register */
__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
/* enabling co-processor CP10 and CP11 accesses in NS world */
__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
per_clocks_enable();
+#ifdef CONFIG_USB_EHCI_OMAP
+ ehci_clocks_enable();
+#endif
+
#ifdef CONFIG_SPL_BUILD
preloader_console_init();
+
+ timer_init();
#endif
if (!in_sdram)
{
/* Workaround for Cortex-A8 errata: #454179 #430973
* Set "IBE" bit
- * Set "Disable Brach Size Mispredicts" bit
+ * Set "Disable Branch Size Mispredicts" bit
* Workaround for erratum #621766
* Enable L1NEON bit
* ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0