ARM: mx5: Enable L2 cache

[oweals/u-boot.git] / arch / arm / cpu / armv7 / mx5 / lowlevel_init.S

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index fc7c76759a77907d234216c62ac5d12d013c9ca8..97077fd367ce846fdce7d426e1fc6e67b927d056 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -31,10 +31,10 @@
 
        /* reconfigure L2 cache aux control reg */
        ldr r0, =0xC0 |                 /* tag RAM */ \
-                0x4 |                  /* data RAM */ \
-                1 << 24 |              /* disable write allocate delay */ \
-                1 << 23 |              /* disable write allocate combine */ \
-                1 << 22                /* disable write allocate */
+                0x4 |                  /* data RAM */ \
+                1 << 24 |              /* disable write allocate delay */ \
+                1 << 23 |              /* disable write allocate combine */ \
+                1 << 22                /* disable write allocate */
 
 #if defined(CONFIG_MX51)
        ldr r3, [r4, #ROM_SI_REV]
@@ -45,6 +45,12 @@
 #endif
 
        mcr 15, 1, r0, c9, c0, 2
+
+       /* enable L2 cache */
+       mrc 15, 0, r0, c1, c0, 1
+       orr r0, r0, #2
+       mcr 15, 0, r0, c1, c0, 1
+
 .endm /* init_l2cc */
 
 /* AIPS setup - Only setup MPROTx registers.
@@ -290,20 +296,20 @@ setup_pll_func:
 
        setup_pll PLL1_BASE_ADDR, 800
 
-        setup_pll PLL3_BASE_ADDR, 400
+       setup_pll PLL3_BASE_ADDR, 400
 
-        /* Switch peripheral to PLL3 */
-        ldr r0, =CCM_BASE_ADDR
-        ldr r1, =0x00015154
-        str r1, [r0, #CLKCTL_CBCMR]
-        ldr r1, =0x02898945
-        str r1, [r0, #CLKCTL_CBCDR]
-        /* make sure change is effective */
+       /* Switch peripheral to PLL3 */
+       ldr r0, =CCM_BASE_ADDR
+       ldr r1, =0x00015154
+       str r1, [r0, #CLKCTL_CBCMR]
+       ldr r1, =0x02898945
+       str r1, [r0, #CLKCTL_CBCDR]
+       /* make sure change is effective */
 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
-        cmp r1, #0x0
-        bne 1b
+       cmp r1, #0x0
+       bne 1b
 
-        setup_pll PLL2_BASE_ADDR, 400
+       setup_pll PLL2_BASE_ADDR, 400
 
        /* Switch peripheral to PLL2 */
        ldr r0, =CCM_BASE_ADDR
@@ -324,7 +330,7 @@ setup_pll_func:
        cmp r1, #0x0
        bne 1b
 
-        setup_pll PLL3_BASE_ADDR, 216
+       setup_pll PLL3_BASE_ADDR, 216
 
        setup_pll PLL4_BASE_ADDR, 455
 
@@ -358,13 +364,13 @@ setup_pll_func:
        str r1, [r0, #CLKCTL_CCGR6]
        str r1, [r0, #CLKCTL_CCGR7]
 
-        mov r1, #0x00000
-        str r1, [r0, #CLKCTL_CCDR]
+       mov r1, #0x00000
+       str r1, [r0, #CLKCTL_CCDR]
 
-        /* for cko - for ARM div by 8 */
-        mov r1, #0x000A0000
-        add r1, r1, #0x00000F0
-        str r1, [r0, #CLKCTL_CCOSR]
+       /* for cko - for ARM div by 8 */
+       mov r1, #0x000A0000
+       add r1, r1, #0x00000F0
+       str r1, [r0, #CLKCTL_CCOSR]
 
 #endif /* CONFIG_MX53 */
 .endm