Merge branch '2020-05-18-reduce-size-of-common.h'

[oweals/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / soc.c

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8d513e096dd4e979497b1df02831037ddc..8a95ee86a9b74b2ba917447a1d71587605c24eff 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -1,10 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <log.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
 #include <asm/arch/fsl_serdes.h>
@@ -12,6 +12,7 @@
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_stream_id.h>
 #include <fsl_csu.h>
+#include <fsl_ddr_sdram.h>
 
 struct liodn_id_table sec_liodn_tbl[] = {
        SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
@@ -60,6 +61,85 @@ unsigned int get_soc_major_rev(void)
        return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+       clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
+                       0xF << 6,
+                       SCFG_USB_TXVREFTUNE << 6);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+       clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
+                       SCFG_USB_SQRXTUNE_MASK << 23);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+       clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
+                       SCFG_USB_PCSTXSWINGFULL_MASK,
+                       SCFG_USB_PCSTXSWINGFULL_VAL);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+       void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
+static void erratum_a008850_early(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+       /* part 1 of 2 */
+       struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+                                               CONFIG_SYS_CCI400_OFFSET);
+       struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+
+       /* disables propagation of barrier transactions to DDRC from CCI400 */
+       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+       /* disable the re-ordering in DDRC */
+       out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+#endif
+}
+
+void erratum_a008850_post(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+       /* part 2 of 2 */
+       struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+                                               CONFIG_SYS_CCI400_OFFSET);
+       struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+       u32 tmp;
+
+       /* enable propagation of barrier transactions to DDRC from CCI400 */
+       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+       /* enable the re-ordering in DDRC */
+       tmp = in_be32(&ddr->eor);
+       tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+       out_be32(&ddr->eor, tmp);
+#endif
+}
+
 void s_init(void)
 {
 }
@@ -80,7 +160,8 @@ void erratum_a010315(void)
 int arch_soc_init(void)
 {
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+                                       CONFIG_SYS_CCI400_OFFSET);
        unsigned int major;
 
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
@@ -91,7 +172,7 @@ int arch_soc_init(void)
        out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
        out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 #endif
 
@@ -119,13 +200,6 @@ int arch_soc_init(void)
                 */
                out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
                out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
-               /* Workaround for the issue that DDR could not respond to
-                * barrier transaction which is generated by executing DSB/ISB
-                * instruction. Set CCI-400 control override register to
-                * terminate the barrier transaction. After DDR is initialized,
-                * allow barrier transaction to DDR again */
-               out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
        }
 
        /* Enable all the snoop signal for various masters */
@@ -146,6 +220,13 @@ int arch_soc_init(void)
         */
        out_be32(&scfg->eddrtqcfg, 0x63b20042);
 
+       /* Erratum */
+       erratum_a008850_early();
+       erratum_a009008();
+       erratum_a009798();
+       erratum_a008997();
+       erratum_a009007();
+
        return 0;
 }