Exynos5: Fix compiler warnings due to clock_get_periph_rate

[oweals/u-boot.git] / arch / arm / cpu / armv7 / exynos / clock.c

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index c0c95fbc83dc805953717b48d8701b15c52f7211..251fc0e9d3141527ffd9a5cdc59046c3c6b014f8 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -20,42 +20,45 @@
  * positions of the peripheral clocks of the src and div registers
  */
 struct clk_bit_info {
+       enum periph_id id;
        int8_t src_bit;
        int8_t div_bit;
        int8_t prediv_bit;
 };
 
-/* src_bit div_bit prediv_bit */
+/* periph_id src_bit div_bit prediv_bit */
 static struct clk_bit_info clk_bit_info[] = {
-       {0,     0,      -1},
-       {4,     4,      -1},
-       {8,     8,      -1},
-       {12,    12,     -1},
-       {0,     0,      8},
-       {4,     16,     24},
-       {8,     0,      8},
-       {12,    16,     24},
-       {-1,    -1,     -1},
-       {16,    0,      8},
-       {20,    16,     24},
-       {24,    0,      8},
-       {0,     0,      4},
-       {4,     12,     16},
-       {-1,    -1,     -1},
-       {-1,    -1,     -1},
-       {-1,    24,     0},
-       {-1,    24,     0},
-       {-1,    24,     0},
-       {-1,    24,     0},
-       {-1,    24,     0},
-       {-1,    24,     0},
-       {-1,    24,     0},
-       {-1,    24,     0},
-       {24,    0,      -1},
-       {24,    0,      -1},
-       {24,    0,      -1},
-       {24,    0,      -1},
-       {24,    0,      -1},
+       {PERIPH_ID_UART0,       0,      0,      -1},
+       {PERIPH_ID_UART1,       4,      4,      -1},
+       {PERIPH_ID_UART2,       8,      8,      -1},
+       {PERIPH_ID_UART3,       12,     12,     -1},
+       {PERIPH_ID_I2C0,        -1,     24,     0},
+       {PERIPH_ID_I2C1,        -1,     24,     0},
+       {PERIPH_ID_I2C2,        -1,     24,     0},
+       {PERIPH_ID_I2C3,        -1,     24,     0},
+       {PERIPH_ID_I2C4,        -1,     24,     0},
+       {PERIPH_ID_I2C5,        -1,     24,     0},
+       {PERIPH_ID_I2C6,        -1,     24,     0},
+       {PERIPH_ID_I2C7,        -1,     24,     0},
+       {PERIPH_ID_SPI0,        16,     0,      8},
+       {PERIPH_ID_SPI1,        20,     16,     24},
+       {PERIPH_ID_SPI2,        24,     0,      8},
+       {PERIPH_ID_SDMMC0,      0,      0,      8},
+       {PERIPH_ID_SDMMC1,      4,      16,     24},
+       {PERIPH_ID_SDMMC2,      8,      0,      8},
+       {PERIPH_ID_SDMMC3,      12,     16,     24},
+       {PERIPH_ID_I2S0,        0,      0,      4},
+       {PERIPH_ID_I2S1,        4,      12,     16},
+       {PERIPH_ID_SPI3,        0,      0,      4},
+       {PERIPH_ID_SPI4,        4,      12,     16},
+       {PERIPH_ID_SDMMC4,      16,     0,      8},
+       {PERIPH_ID_PWM0,        24,     0,      -1},
+       {PERIPH_ID_PWM1,        24,     0,      -1},
+       {PERIPH_ID_PWM2,        24,     0,      -1},
+       {PERIPH_ID_PWM3,        24,     0,      -1},
+       {PERIPH_ID_PWM4,        24,     0,      -1},
+
+       {PERIPH_ID_NONE,        -1,     -1,     -1},
 };
 
 /* Epll Clock division values to achive different frequency output */
@@ -118,7 +121,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
                        div = PLL_DIV_1024;
                else if (proid_is_exynos4412())
                        div = PLL_DIV_65535;
-               else if (proid_is_exynos5250() || proid_is_exynos5420())
+               else if (proid_is_exynos5250() || proid_is_exynos5420()
+                        || proid_is_exynos5800())
                        div = PLL_DIV_65536;
                else
                        return 0;
@@ -259,9 +263,24 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
        return fout;
 }
 
+static struct clk_bit_info *get_clk_bit_info(int peripheral)
+{
+       int i;
+
+       for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
+               if (clk_bit_info[i].id == peripheral)
+                       break;
+       }
+
+       if (clk_bit_info[i].id == PERIPH_ID_NONE)
+               debug("ERROR: Peripheral ID %d not found\n", peripheral);
+
+       return &clk_bit_info[i];
+}
+
 static unsigned long exynos5_get_periph_rate(int peripheral)
 {
-       struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
+       struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
        unsigned long sclk, sub_clk;
        unsigned int src, div, sub_div;
        struct exynos5_clock *clk =
@@ -847,6 +866,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index)
 
        if (sel == 0x3)
                sclk = get_pll_clk(MPLL);
+       else if (sel == 0x4)
+               sclk = get_pll_clk(SPLL);
        else if (sel == 0x6)
                sclk = get_pll_clk(EPLL);
        else
@@ -1581,7 +1602,7 @@ static unsigned long exynos4_get_i2c_clk(void)
 unsigned long get_pll_clk(int pllreg)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_pll_clk(pllreg);
                return exynos5_get_pll_clk(pllreg);
        } else {
@@ -1617,7 +1638,7 @@ unsigned long get_i2c_clk(void)
 unsigned long get_pwm_clk(void)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_pwm_clk();
                return clock_get_periph_rate(PERIPH_ID_PWM0);
        } else {
@@ -1630,7 +1651,7 @@ unsigned long get_pwm_clk(void)
 unsigned long get_uart_clk(int dev_index)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_uart_clk(dev_index);
                return exynos5_get_uart_clk(dev_index);
        } else {
@@ -1643,7 +1664,7 @@ unsigned long get_uart_clk(int dev_index)
 unsigned long get_mmc_clk(int dev_index)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_mmc_clk(dev_index);
                return exynos5_get_mmc_clk(dev_index);
        } else {
@@ -1653,8 +1674,12 @@ unsigned long get_mmc_clk(int dev_index)
 
 void set_mmc_clk(int dev_index, unsigned int div)
 {
+       /* If want to set correct value, it needs to substract one from div.*/
+       if (div > 0)
+               div -= 1;
+
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        exynos5420_set_mmc_clk(dev_index, div);
                else
                        exynos5_set_mmc_clk(dev_index, div);
@@ -1668,7 +1693,7 @@ unsigned long get_lcd_clk(void)
        if (cpu_is_exynos4())
                return exynos4_get_lcd_clk();
        else {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_lcd_clk();
                else
                        return exynos5_get_lcd_clk();
@@ -1682,7 +1707,7 @@ void set_lcd_clk(void)
        else {
                if (proid_is_exynos5250())
                        exynos5_set_lcd_clk();
-               else if (proid_is_exynos5420())
+               else if (proid_is_exynos5420() || proid_is_exynos5800())
                        exynos5420_set_lcd_clk();
        }
 }
@@ -1696,7 +1721,7 @@ void set_mipi_clk(void)
 int set_spi_clk(int periph_id, unsigned int rate)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_set_spi_clk(periph_id, rate);
                return exynos5_set_spi_clk(periph_id, rate);
        } else {