* positions of the peripheral clocks of the src and div registers
*/
struct clk_bit_info {
+ enum periph_id id;
int8_t src_bit;
int8_t div_bit;
int8_t prediv_bit;
};
-/* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[] = {
- {0, 0, -1},
- {4, 4, -1},
- {8, 8, -1},
- {12, 12, -1},
- {0, 0, 8},
- {4, 16, 24},
- {8, 0, 8},
- {12, 16, 24},
- {-1, -1, -1},
- {16, 0, 8},
- {20, 16, 24},
- {24, 0, 8},
- {0, 0, 4},
- {4, 12, 16},
- {-1, -1, -1},
- {-1, -1, -1},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
+/* periph_id src_bit div_bit prediv_bit */
+static struct clk_bit_info exynos5_bit_info[] = {
+ {PERIPH_ID_UART0, 0, 0, -1},
+ {PERIPH_ID_UART1, 4, 4, -1},
+ {PERIPH_ID_UART2, 8, 8, -1},
+ {PERIPH_ID_UART3, 12, 12, -1},
+ {PERIPH_ID_I2C0, -1, 24, 0},
+ {PERIPH_ID_I2C1, -1, 24, 0},
+ {PERIPH_ID_I2C2, -1, 24, 0},
+ {PERIPH_ID_I2C3, -1, 24, 0},
+ {PERIPH_ID_I2C4, -1, 24, 0},
+ {PERIPH_ID_I2C5, -1, 24, 0},
+ {PERIPH_ID_I2C6, -1, 24, 0},
+ {PERIPH_ID_I2C7, -1, 24, 0},
+ {PERIPH_ID_SPI0, 16, 0, 8},
+ {PERIPH_ID_SPI1, 20, 16, 24},
+ {PERIPH_ID_SPI2, 24, 0, 8},
+ {PERIPH_ID_SDMMC0, 0, 0, 8},
+ {PERIPH_ID_SDMMC1, 4, 16, 24},
+ {PERIPH_ID_SDMMC2, 8, 0, 8},
+ {PERIPH_ID_SDMMC3, 12, 16, 24},
+ {PERIPH_ID_I2S0, 0, 0, 4},
+ {PERIPH_ID_I2S1, 4, 12, 16},
+ {PERIPH_ID_SPI3, 0, 0, 4},
+ {PERIPH_ID_SPI4, 4, 12, 16},
+ {PERIPH_ID_SDMMC4, 16, 0, 8},
+ {PERIPH_ID_PWM0, 24, 0, -1},
+ {PERIPH_ID_PWM1, 24, 0, -1},
+ {PERIPH_ID_PWM2, 24, 0, -1},
+ {PERIPH_ID_PWM3, 24, 0, -1},
+ {PERIPH_ID_PWM4, 24, 0, -1},
+
+ {PERIPH_ID_NONE, -1, -1, -1},
+};
+
+static struct clk_bit_info exynos542x_bit_info[] = {
+ {PERIPH_ID_UART0, 4, 8, -1},
+ {PERIPH_ID_UART1, 8, 12, -1},
+ {PERIPH_ID_UART2, 12, 16, -1},
+ {PERIPH_ID_UART3, 16, 20, -1},
+ {PERIPH_ID_I2C0, -1, 8, -1},
+ {PERIPH_ID_I2C1, -1, 8, -1},
+ {PERIPH_ID_I2C2, -1, 8, -1},
+ {PERIPH_ID_I2C3, -1, 8, -1},
+ {PERIPH_ID_I2C4, -1, 8, -1},
+ {PERIPH_ID_I2C5, -1, 8, -1},
+ {PERIPH_ID_I2C6, -1, 8, -1},
+ {PERIPH_ID_I2C7, -1, 8, -1},
+ {PERIPH_ID_SPI0, 20, 20, 8},
+ {PERIPH_ID_SPI1, 24, 24, 16},
+ {PERIPH_ID_SPI2, 28, 28, 24},
+ {PERIPH_ID_SDMMC0, 8, 0, -1},
+ {PERIPH_ID_SDMMC1, 12, 10, -1},
+ {PERIPH_ID_SDMMC2, 16, 20, -1},
+ {PERIPH_ID_I2C8, -1, 8, -1},
+ {PERIPH_ID_I2C9, -1, 8, -1},
+ {PERIPH_ID_I2S0, 0, 0, 4},
+ {PERIPH_ID_I2S1, 4, 12, 16},
+ {PERIPH_ID_SPI3, 12, 16, 0},
+ {PERIPH_ID_SPI4, 16, 20, 8},
+ {PERIPH_ID_PWM0, 24, 28, -1},
+ {PERIPH_ID_PWM1, 24, 28, -1},
+ {PERIPH_ID_PWM2, 24, 28, -1},
+ {PERIPH_ID_PWM3, 24, 28, -1},
+ {PERIPH_ID_PWM4, 24, 28, -1},
+ {PERIPH_ID_I2C10, -1, 8, -1},
+
+ {PERIPH_ID_NONE, -1, -1, -1},
};
/* Epll Clock division values to achive different frequency output */
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
- else if (proid_is_exynos5250() || proid_is_exynos5420())
+ else if (proid_is_exynos5250() || proid_is_exynos5420()
+ || proid_is_exynos5800())
div = PLL_DIV_65536;
else
return 0;
return fout;
}
+/* exynos542x: return pll clock frequency */
+static unsigned long exynos542x_get_pll_clk(int pllreg)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
+ case RPLL:
+ r = readl(&clk->rpll_con0);
+ k = readl(&clk->rpll_con1);
+ break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
+static struct clk_bit_info *get_clk_bit_info(int peripheral)
+{
+ int i;
+ struct clk_bit_info *info;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ info = exynos542x_bit_info;
+ else
+ info = exynos5_bit_info;
+
+ for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
+ if (info[i].id == peripheral)
+ break;
+ }
+
+ if (info[i].id == PERIPH_ID_NONE)
+ debug("ERROR: Peripheral ID %d not found\n", peripheral);
+
+ return &info[i];
+}
+
static unsigned long exynos5_get_periph_rate(int peripheral)
{
- struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
- unsigned long sclk, sub_clk;
- unsigned int src, div, sub_div;
+ struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+ unsigned long sclk, sub_clk = 0;
+ unsigned int src, div, sub_div = 0;
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
+ src = readl(&clk->src_fsys);
+ div = readl(&clk->div_fsys1);
+ break;
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
- div = readl(&clk->div_fsys1);
+ div = readl(&clk->div_fsys2);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
return -1;
};
- src = (src >> bit_info->src_bit) & 0xf;
+ if (bit_info->src_bit >= 0)
+ src = (src >> bit_info->src_bit) & 0xf;
switch (src) {
case EXYNOS_SRC_MPLL:
}
/* Ratio clock division for this peripheral */
- sub_div = (div >> bit_info->div_bit) & 0xf;
- sub_clk = sclk / (sub_div + 1);
+ if (bit_info->div_bit >= 0) {
+ sub_div = (div >> bit_info->div_bit) & 0xf;
+ sub_clk = sclk / (sub_div + 1);
+ }
- /* Pre-ratio clock division for SDMMC0 and 2 */
- if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
+ if (bit_info->prediv_bit >= 0) {
div = (div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (div + 1);
}
return sub_clk;
}
-unsigned long clock_get_periph_rate(int peripheral)
-{
- if (cpu_is_exynos5())
- return exynos5_get_periph_rate(peripheral);
- else
- return 0;
-}
-
-/* exynos5420: return pll clock frequency */
-static unsigned long exynos5420_get_pll_clk(int pllreg)
+static unsigned long exynos542x_get_periph_rate(int peripheral)
{
+ struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+ unsigned long sclk, sub_clk = 0;
+ unsigned int src, div, sub_div = 0;
struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
+ (struct exynos5420_clock *)samsung_get_base_clock();
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ case PERIPH_ID_PWM4:
+ src = readl(&clk->src_peric0);
+ div = readl(&clk->div_peric0);
break;
- case MPLL:
- r = readl(&clk->mpll_con0);
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ src = readl(&clk->src_peric1);
+ div = readl(&clk->div_peric1);
+ sub_div = readl(&clk->div_peric4);
break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ src = readl(&clk->src_isp);
+ div = readl(&clk->div_isp1);
+ sub_div = readl(&clk->div_isp1);
break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ src = readl(&clk->src_fsys);
+ div = readl(&clk->div_fsys1);
break;
- case BPLL:
- r = readl(&clk->bpll_con0);
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ case PERIPH_ID_I2C8:
+ case PERIPH_ID_I2C9:
+ case PERIPH_ID_I2C10:
+ sclk = exynos542x_get_pll_clk(MPLL);
+ sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
+ & 0x7) + 1;
+ return sclk / sub_div;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ };
+
+ if (bit_info->src_bit >= 0)
+ src = (src >> bit_info->src_bit) & 0xf;
+
+ switch (src) {
+ case EXYNOS542X_SRC_MPLL:
+ sclk = exynos542x_get_pll_clk(MPLL);
break;
- case RPLL:
- r = readl(&clk->rpll_con0);
- k = readl(&clk->rpll_con1);
+ case EXYNOS542X_SRC_SPLL:
+ sclk = exynos542x_get_pll_clk(SPLL);
break;
- case SPLL:
- r = readl(&clk->spll_con0);
+ case EXYNOS542X_SRC_EPLL:
+ sclk = exynos542x_get_pll_clk(EPLL);
+ break;
+ case EXYNOS542X_SRC_RPLL:
+ sclk = exynos542x_get_pll_clk(RPLL);
break;
default:
- printf("Unsupported PLL (%d)\n", pllreg);
return 0;
}
- return exynos_get_pll_clk(pllreg, r, k);
+ /* Ratio clock division for this peripheral */
+ if (bit_info->div_bit >= 0) {
+ div = (div >> bit_info->div_bit) & 0xf;
+ sub_clk = sclk / (div + 1);
+ }
+
+ if (bit_info->prediv_bit >= 0) {
+ sub_div = (sub_div >> bit_info->prediv_bit) & 0xff;
+ return sub_clk / (sub_div + 1);
+ }
+
+ return sub_clk;
+}
+
+unsigned long clock_get_periph_rate(int peripheral)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos542x_get_periph_rate(peripheral);
+ return exynos5_get_periph_rate(peripheral);
+ } else {
+ return 0;
+ }
}
/* exynos4: return ARM clock frequency */
if (sel == 0x3)
sclk = get_pll_clk(MPLL);
+ else if (sel == 0x4)
+ sclk = get_pll_clk(SPLL);
else if (sel == 0x6)
sclk = get_pll_clk(EPLL);
else
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
- return exynos5420_get_pll_clk(pllreg);
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos542x_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
if (proid_is_exynos4412())
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
unsigned long get_uart_clk(int dev_index)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
} else {
unsigned long get_mmc_clk(int dev_index)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
} else {
void set_mmc_clk(int dev_index, unsigned int div)
{
+ /* If want to set correct value, it needs to substract one from div.*/
+ if (div > 0)
+ div -= 1;
+
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);
else
exynos5_set_mmc_clk(dev_index, div);
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_lcd_clk();
else
return exynos5_get_lcd_clk();
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
- else if (proid_is_exynos5420())
+ else if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_lcd_clk();
}
}
int set_spi_clk(int periph_id, unsigned int rate)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
} else {
projects / oweals / u-boot.git / blobdiff