ARM: OMAP5: Add functions to enable and disable EDMA3 clocks

[oweals/u-boot.git] / arch / arm / cpu / armv7 / cpu.c

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index c56417dd2f1ec81d8fa1088d8c12fc0aaf6c3848..0b0e5003cc3c390e9cb86fe13d8426e5840ae731 100644 (file)
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -24,7 +24,7 @@
 
 void __weak cpu_cache_initialization(void){}
 
-int cleanup_before_linux(void)
+int cleanup_before_linux_select(int flags)
 {
        /*
         * this function is called just before we call linux
@@ -42,24 +42,30 @@ int cleanup_before_linux(void)
        icache_disable();
        invalidate_icache_all();
 
-       /*
-        * turn off D-cache
-        * dcache_disable() in turn flushes the d-cache and disables MMU
-        */
-       dcache_disable();
-       v7_outer_cache_disable();
+       if (flags & CBL_DISABLE_CACHES) {
+               /*
+               * turn off D-cache
+               * dcache_disable() in turn flushes the d-cache and disables MMU
+               */
+               dcache_disable();
+               v7_outer_cache_disable();
 
-       /*
-        * After D-cache is flushed and before it is disabled there may
-        * be some new valid entries brought into the cache. We are sure
-        * that these lines are not dirty and will not affect our execution.
-        * (because unwinding the call-stack and setting a bit in CP15 SCTLR
-        * is all we did during this. We have not pushed anything on to the
-        * stack. Neither have we affected any static data)
-        * So just invalidate the entire d-cache again to avoid coherency
-        * problems for kernel
-        */
-       invalidate_dcache_all();
+               /*
+               * After D-cache is flushed and before it is disabled there may
+               * be some new valid entries brought into the cache. We are
+               * sure that these lines are not dirty and will not affect our
+               * execution. (because unwinding the call-stack and setting a
+               * bit in CP15 SCTRL is all we did during this. We have not
+               * pushed anything on to the stack. Neither have we affected
+               * any static data) So just invalidate the entire d-cache again
+               * to avoid coherency problems for kernel
+               */
+               invalidate_dcache_all();
+       } else {
+               flush_dcache_all();
+               invalidate_icache_all();
+               icache_enable();
+       }
 
        /*
         * Some CPU need more cache attention before starting the kernel.
@@ -68,3 +74,8 @@ int cleanup_before_linux(void)
 
        return 0;
 }
+
+int cleanup_before_linux(void)
+{
+       return cleanup_before_linux_select(CBL_ALL);
+}