{
u32 mva;
- /*
- * If start address is not aligned to cache-line do not
- * invalidate the first cache-line
- */
- if (start & (line_len - 1)) {
- printf("ERROR: %s - start address is not aligned - 0x%08x\n",
- __func__, start);
- /* move to next cache line */
- start = (start + line_len - 1) & ~(line_len - 1);
- }
-
- /*
- * If stop address is not aligned to cache-line do not
- * invalidate the last cache-line
- */
- if (stop & (line_len - 1)) {
- printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
- __func__, stop);
- /* align to the beginning of this cache line */
- stop &= ~(line_len - 1);
- }
+ if (!check_cache_range(start, stop))
+ return;
for (mva = start; mva < stop; mva = mva + line_len) {
/* DCIMVAC - Invalidate data cache by MVA to PoC */
}
/* DSB to make sure the operation is complete */
- DSB;
+ dsb();
}
/* Invalidate TLB */
/* Invalidate entire instruction TLB */
asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- DSB;
+ dsb();
/* Full system ISB - make sure the instruction stream sees it */
- ISB;
+ isb();
}
void invalidate_dcache_all(void)
asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- DSB;
+ dsb();
/* ISB - make sure the instruction stream sees it */
- ISB;
+ isb();
}
#else
void invalidate_icache_all(void)