Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master'

[oweals/u-boot.git] / arch / arm / cpu / armv7 / cache_v7.c

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 665f025b6f598fde57ebc1634b5a54f8b33824a1..a2c4032fed8c2c8d7719f4be0806319ac077261a 100644 (file)
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -3,23 +3,7 @@
  * Texas Instruments, <www.ti.com>
  * Aneesh V <aneesh@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <linux/types.h>
 #include <common.h>
@@ -181,21 +165,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
        u32 mva;
 
        /*
-        * If start address is not aligned to cache-line flush the first
-        * line to prevent affecting somebody else's buffer
+        * If start address is not aligned to cache-line do not
+        * invalidate the first cache-line
         */
        if (start & (line_len - 1)) {
-               v7_dcache_clean_inval_range(start, start + 1, line_len);
+               printf("ERROR: %s - start address is not aligned - 0x%08x\n",
+                       __func__, start);
                /* move to next cache line */
                start = (start + line_len - 1) & ~(line_len - 1);
        }
 
        /*
-        * If stop address is not aligned to cache-line flush the last
-        * line to prevent affecting somebody else's buffer
+        * If stop address is not aligned to cache-line do not
+        * invalidate the last cache-line
         */
        if (stop & (line_len - 1)) {
-               v7_dcache_clean_inval_range(stop, stop + 1, line_len);
+               printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
+                       __func__, stop);
                /* align to the beginning of this cache line */
                stop &= ~(line_len - 1);
        }
@@ -295,6 +281,12 @@ void arm_init_before_mmu(void)
        v7_inval_tlb();
 }
 
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+       flush_dcache_range(start, stop);
+       v7_inval_tlb();
+}
+
 /*
  * Flush range from all levels of d-cache/unified-cache used:
  * Affects the range [start, start + size - 1]
@@ -327,6 +319,14 @@ void arm_init_before_mmu(void)
 void  flush_cache(unsigned long start, unsigned long size)
 {
 }
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+
+void arm_init_domains(void)
+{
+}
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 #ifndef CONFIG_SYS_ICACHE_OFF
@@ -354,41 +354,10 @@ void invalidate_icache_all(void)
 }
 #endif
 
-/*
- * Stub implementations for outer cache operations
- */
-void __v7_outer_cache_enable(void)
-{
-}
-void v7_outer_cache_enable(void)
-       __attribute__((weak, alias("__v7_outer_cache_enable")));
-
-void __v7_outer_cache_disable(void)
-{
-}
-void v7_outer_cache_disable(void)
-       __attribute__((weak, alias("__v7_outer_cache_disable")));
-
-void __v7_outer_cache_flush_all(void)
-{
-}
-void v7_outer_cache_flush_all(void)
-       __attribute__((weak, alias("__v7_outer_cache_flush_all")));
-
-void __v7_outer_cache_inval_all(void)
-{
-}
-void v7_outer_cache_inval_all(void)
-       __attribute__((weak, alias("__v7_outer_cache_inval_all")));
-
-void __v7_outer_cache_flush_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_flush_range(u32 start, u32 end)
-       __attribute__((weak, alias("__v7_outer_cache_flush_range")));
-
-void __v7_outer_cache_inval_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_inval_range(u32 start, u32 end)
-       __attribute__((weak, alias("__v7_outer_cache_inval_range")));
+/*  Stub implementations for outer cache operations */
+__weak void v7_outer_cache_enable(void) {}
+__weak void v7_outer_cache_disable(void) {}
+__weak void v7_outer_cache_flush_all(void) {}
+__weak void v7_outer_cache_inval_all(void) {}
+__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
+__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}