+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
-#include <version.h>
/*
*************************************************************************
/*
* disable MMU and D cache
- * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+ * enable I cache if SYS_ICACHE_OFF is not defined
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
#else
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
-#ifndef CONFIG_SYS_ICACHE_OFF
+ orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Go setup Memory and board specific bits prior to relocation.
*/
- mov ip, lr /* perserve link reg across call */
+ mov r4, lr /* perserve link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
- mov lr, ip /* restore link */
+ mov lr, r4 /* restore link */
+#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */