DaVinci DA8xx: fix set_cpu_clk_info()

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / pantheon / cpu.c

diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
index 9ddc77c0718c4ffb489f87e82a13ed0894a94ffb..db9b348ad3bf4f3b25589d5864bc49d314daf786 100644 (file)
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -23,8 +23,8 @@
  */
 
 #include <common.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/pantheon.h>
-#include <asm/io.h>
 
 #define UARTCLK14745KHZ        (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
 #define SET_MRVL_ID    (1<<8)
@@ -42,6 +42,9 @@ int arch_cpu_init(void)
        struct panthmpmu_registers *mpmu =
                (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
 
+       struct panthapmu_registers *apmu =
+               (struct panthapmu_registers *) PANTHEON_APMU_BASE;
+
        /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
        val = readl(&cpuregs->cpu_conf);
        val = val | SET_MRVL_ID;
@@ -59,6 +62,20 @@ int arch_cpu_init(void)
        /* Enable GPIO clock */
        writel(APBC_APBCLK, &apbclkres->gpio);
 
+#ifdef CONFIG_I2C_MV
+       /* Enable I2C clock */
+       writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+       writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+#endif
+
+#ifdef CONFIG_MV_SDHCI
+       /* Enable mmc clock */
+       writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+                       &apmu->sd1);
+       writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+                       &apmu->sd3);
+#endif
+
        icache_enable();
 
        return 0;
@@ -76,3 +93,9 @@ int print_cpuinfo(void)
        return 0;
 }
 #endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif