Merge samsung, imx, tegra into u-boot-arm/master

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / spl_mem_init.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index cca131688b6f54fe7f497e317f736281f54afedf..401c51362bfd6bf6c0c04a68dce15973adcfe20a 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -26,12 +26,15 @@
 #include <common.h>
 #include <config.h>
 #include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
 #include <asm/arch/imx-regs.h>
 
-#include "mx28_init.h"
+#include "mxs_init.h"
 
-static uint32_t mx28_dram_vals[] = {
+static uint32_t dram_vals[] = {
+/*
+ * i.MX28 DDR2 at 200MHz
+ */
+#if defined(CONFIG_MX28)
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -80,28 +83,31 @@ static uint32_t mx28_dram_vals[] = {
        0x06120612, 0x04320432, 0x04320432, 0x00040004,
        0x00040004, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00010001
+#else
+#error Unsupported memory initialization
+#endif
 };
 
-void __mx28_adjust_memory_params(uint32_t *dram_vals)
+void __mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 }
-void mx28_adjust_memory_params(uint32_t *dram_vals)
-       __attribute__((weak, alias("__mx28_adjust_memory_params")));
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+       __attribute__((weak, alias("__mxs_adjust_memory_params")));
 
-void init_mx28_200mhz_ddr2(void)
+static void initialize_dram_values(void)
 {
        int i;
 
-       mx28_adjust_memory_params(mx28_dram_vals);
+       mxs_adjust_memory_params(dram_vals);
 
-       for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
-               writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
+       for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+               writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
 
-void mx28_mem_init_clock(void)
+static void mxs_mem_init_clock(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        /* Gate EMI clock */
        writeb(CLKCTRL_FRAC_CLKGATE,
@@ -129,10 +135,10 @@ void mx28_mem_init_clock(void)
        early_delay(10000);
 }
 
-void mx28_mem_setup_cpu_and_hbus(void)
+static void mxs_mem_setup_cpu_and_hbus(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
         * and ungate CPU clock */
@@ -161,10 +167,10 @@ void mx28_mem_setup_cpu_and_hbus(void)
        early_delay(15000);
 }
 
-void mx28_mem_setup_vdda(void)
+static void mxs_mem_setup_vdda(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
                (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
@@ -172,18 +178,7 @@ void mx28_mem_setup_vdda(void)
                &power_regs->hw_power_vddactrl);
 }
 
-void mx28_mem_setup_vddd(void)
-{
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
-
-       writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
-               (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
-               POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
-               &power_regs->hw_power_vdddctrl);
-}
-
-uint32_t mx28_mem_get_size(void)
+uint32_t mxs_mem_get_size(void)
 {
        uint32_t sz, da;
        uint32_t *vt = (uint32_t *)0x20;
@@ -202,12 +197,12 @@ uint32_t mx28_mem_get_size(void)
        return sz;
 }
 
-void mx28_mem_init(void)
+void mxs_mem_init(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-       struct mx28_pinctrl_regs *pinctrl_regs =
-               (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_pinctrl_regs *pinctrl_regs =
+               (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
 
        /* Set DDR2 mode */
        writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
@@ -219,9 +214,9 @@ void mx28_mem_init(void)
 
        early_delay(11000);
 
-       mx28_mem_init_clock();
+       mxs_mem_init_clock();
 
-       mx28_mem_setup_vdda();
+       mxs_mem_setup_vdda();
 
        /*
         * Configure the DRAM registers
@@ -230,7 +225,7 @@ void mx28_mem_init(void)
        /* Clear START bit from DRAM_CTL16 */
        clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
 
-       init_mx28_200mhz_ddr2();
+       initialize_dram_values();
 
        /* Clear SREFRESH bit from DRAM_CTL17 */
        clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
@@ -242,9 +237,7 @@ void mx28_mem_init(void)
        while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
                ;
 
-       mx28_mem_setup_vddd();
-
        early_delay(10000);
 
-       mx28_mem_setup_cpu_and_hbus();
+       mxs_mem_setup_cpu_and_hbus();
 }