Merge branch 'agust@denx.de-next' of git://git.denx.de/u-boot-staging

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / mxs.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index a61f75be8c33374da1405802436f78adfa3a7a69..6ce8019b835ef832a2dfdab056f8bc7215b73aec 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR;
 /* 1 second delay should be plenty of time for block reset. */
 #define        RESET_MAX_TIMEOUT       1000000
 
-#define        MX28_BLOCK_SFTRST       (1 << 31)
-#define        MX28_BLOCK_CLKGATE      (1 << 30)
+#define        MXS_BLOCK_SFTRST        (1 << 31)
+#define        MXS_BLOCK_CLKGATE       (1 << 30)
 
 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 inline void lowlevel_init(void) {}
@@ -81,7 +81,8 @@ void enable_caches(void)
 #endif
 }
 
-int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+                                                               int timeout)
 {
        while (--timeout) {
                if ((readl(&reg->reg) & mask) == mask)
@@ -92,7 +93,8 @@ int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
        return !timeout;
 }
 
-int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+                                                               int timeout)
 {
        while (--timeout) {
                if ((readl(&reg->reg) & mask) == 0)
@@ -103,34 +105,34 @@ int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
        return !timeout;
 }
 
-int mx28_reset_block(struct mxs_register_32 *reg)
+int mxs_reset_block(struct mxs_register_32 *reg)
 {
        /* Clear SFTRST */
-       writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+       writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
 
-       if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+       if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
                return 1;
 
        /* Clear CLKGATE */
-       writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+       writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
 
        /* Set SFTRST */
-       writel(MX28_BLOCK_SFTRST, &reg->reg_set);
+       writel(MXS_BLOCK_SFTRST, &reg->reg_set);
 
        /* Wait for CLKGATE being set */
-       if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+       if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
                return 1;
 
        /* Clear SFTRST */
-       writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+       writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
 
-       if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+       if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
                return 1;
 
        /* Clear CLKGATE */
-       writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+       writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
 
-       if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+       if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
                return 1;
 
        return 0;
@@ -229,7 +231,7 @@ int print_cpuinfo(void)
                get_cpu_type(),
                get_cpu_rev(),
                mxc_get_clock(MXC_ARM_CLK) / 1000000);
-       printf("BOOT:  %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
+       printf("BOOT:  %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
        return 0;
 }
 #endif
@@ -246,7 +248,7 @@ int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 /*
  * Initializes on-chip ethernet controllers.
  */
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
 int cpu_eth_init(bd_t *bis)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
@@ -299,7 +301,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 
        writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
 
-       if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+       if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
                                MXS_OCOTP_MAX_TIMEOUT)) {
                printf("MXS FEC: Can't get MAC from OCOTP\n");
                return;
@@ -320,13 +322,13 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif
 
-int mx28_dram_init(void)
+int mxs_dram_init(void)
 {
        struct mxs_spl_data *data = (struct mxs_spl_data *)
                ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
 
        if (data->mem_dram_size == 0) {
-               printf("MX28:\n"
+               printf("MXS:\n"
                        "Error, the RAM size passed up from SPL is 0!\n");
                hang();
        }