mxs: Clarify why we poweroff in case of brownout in 5v conflict

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / clock.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 0439f9c0eae1a4209b2dd914bb357941f057b758..bfea6abeb0714e38dc02351bb32fd6ec7031fef2 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -43,8 +43,8 @@
 
 static uint32_t mx28_get_pclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -75,8 +75,8 @@ static uint32_t mx28_get_pclk(void)
 
 static uint32_t mx28_get_hclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t div;
        uint32_t clkctrl;
@@ -93,8 +93,8 @@ static uint32_t mx28_get_hclk(void)
 
 static uint32_t mx28_get_emiclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -118,8 +118,8 @@ static uint32_t mx28_get_emiclk(void)
 
 static uint32_t mx28_get_gpmiclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -145,8 +145,8 @@ static uint32_t mx28_get_gpmiclk(void)
  */
 void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t div;
        int io_reg;
 
@@ -178,8 +178,8 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
  */
 static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint8_t ret;
        int io_reg;
 
@@ -199,15 +199,15 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
  */
 void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t clk, clkreg;
 
        if (ssp > MXC_SSPCLK3)
                return;
 
        clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-                       (ssp * sizeof(struct mx28_register_32));
+                       (ssp * sizeof(struct mxs_register_32));
 
        clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
        while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
@@ -243,8 +243,8 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
  */
 static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t clkreg;
        uint32_t clk, tmp;
 
@@ -256,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
                return XTAL_FREQ_KHZ;
 
        clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-                       (ssp * sizeof(struct mx28_register_32));
+                       (ssp * sizeof(struct mxs_register_32));
 
        tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
 
@@ -273,12 +273,12 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
  */
 void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
 {
-       struct mx28_ssp_regs *ssp_regs;
+       struct mxs_ssp_regs *ssp_regs;
        const uint32_t sspclk = mx28_get_sspclk(bus);
        uint32_t reg;
        uint32_t divide, rate, tgtclk;
 
-       ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+       ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
 
        /*
         * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),