Merge samsung, imx, tegra into u-boot-arm/master

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / clock.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 3e29c56e8bc3ad63c724fad790ca4b33d3379315..4ff19c37efe91ac7247f2b48c0d78097de9fd9e1 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -43,8 +43,8 @@
 
 static uint32_t mx28_get_pclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -75,8 +75,8 @@ static uint32_t mx28_get_pclk(void)
 
 static uint32_t mx28_get_hclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t div;
        uint32_t clkctrl;
@@ -93,8 +93,8 @@ static uint32_t mx28_get_hclk(void)
 
 static uint32_t mx28_get_emiclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -118,8 +118,8 @@ static uint32_t mx28_get_emiclk(void)
 
 static uint32_t mx28_get_gpmiclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -145,8 +145,8 @@ static uint32_t mx28_get_gpmiclk(void)
  */
 void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t div;
        int io_reg;
 
@@ -178,8 +178,8 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
  */
 static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint8_t ret;
        int io_reg;
 
@@ -199,8 +199,8 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
  */
 void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t clk, clkreg;
 
        if (ssp > MXC_SSPCLK3)
@@ -243,8 +243,8 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
  */
 static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t clkreg;
        uint32_t clk, tmp;
 
@@ -273,12 +273,12 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
  */
 void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
 {
-       struct mx28_ssp_regs *ssp_regs;
+       struct mxs_ssp_regs *ssp_regs;
        const uint32_t sspclk = mx28_get_sspclk(bus);
        uint32_t reg;
        uint32_t divide, rate, tgtclk;
 
-       ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+       ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
 
        /*
         * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
@@ -333,6 +333,8 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
                return mx28_get_sspclk(MXC_SSPCLK2);
        case MXC_SSP3_CLK:
                return mx28_get_sspclk(MXC_SSPCLK3);
+       case MXC_XTAL_CLK:
+               return XTAL_FREQ_KHZ * 1000;
        }
 
        return 0;