arm/davinci/da850: add uart0 pinmux

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / mx28 / spl_mem_init.c

diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index 4af9eb7dbc0840ef6334900cd4485e1972ec0c78..e17a4d7c7fb60caefe8c1f1a568d419aa5360e22 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -82,10 +82,18 @@ uint32_t dram_vals[] = {
        0x00000000, 0x00010001
 };
 
+void __mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+}
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+       __attribute__((weak, alias("__mx28_adjust_memory_params")));
+
 void init_m28_200mhz_ddr2(void)
 {
        int i;
 
+       mx28_adjust_memory_params(dram_vals);
+
        for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
                writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
@@ -96,22 +104,20 @@ void mx28_mem_init_clock(void)
                (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        /* Gate EMI clock */
-       writel(CLKCTRL_FRAC0_CLKGATEEMI,
-               &clkctrl_regs->hw_clkctrl_frac0_set);
+       writeb(CLKCTRL_FRAC_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
 
-       /* EMI = 205MHz */
-       writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
-               &clkctrl_regs->hw_clkctrl_frac0_set);
-       writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
-               CLKCTRL_FRAC0_EMIFRAC_MASK,
-               &clkctrl_regs->hw_clkctrl_frac0_clr);
+       /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
+       writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
+               &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
 
        /* Ungate EMI clock */
-       writel(CLKCTRL_FRAC0_CLKGATEEMI,
-               &clkctrl_regs->hw_clkctrl_frac0_clr);
+       writeb(CLKCTRL_FRAC_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
 
        early_delay(11000);
 
+       /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
        writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
                (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
                &clkctrl_regs->hw_clkctrl_emi);
@@ -128,10 +134,10 @@ void mx28_mem_setup_cpu_and_hbus(void)
        struct mx28_clkctrl_regs *clkctrl_regs =
                (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-       /* CPU = 454MHz and ungate CPU clock */
-       clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-               CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
-               19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
+       /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
+        * and ungate CPU clock */
+       writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
+               (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
 
        /* Set CPU bypass */
        writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
@@ -151,6 +157,8 @@ void mx28_mem_setup_cpu_and_hbus(void)
        /* Disable CPU bypass */
        writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
                &clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+       early_delay(15000);
 }
 
 void mx28_mem_setup_vdda(void)
@@ -175,29 +183,23 @@ void mx28_mem_setup_vddd(void)
                &power_regs->hw_power_vdddctrl);
 }
 
-void data_abort_memdetect_handler(void) __attribute__((naked));
-void data_abort_memdetect_handler(void)
+uint32_t mx28_mem_get_size(void)
 {
-       asm volatile("subs pc, r14, #4");
-}
-
-void mx28_mem_get_size(void)
-{
-       struct mx28_digctl_regs *digctl_regs =
-               (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
        uint32_t sz, da;
        uint32_t *vt = (uint32_t *)0x20;
+       /* The following is "subs pc, r14, #4", used as return from DABT. */
+       const uint32_t data_abort_memdetect_handler = 0xe25ef004;
 
        /* Replace the DABT handler. */
        da = vt[4];
-       vt[4] = (uint32_t)&data_abort_memdetect_handler;
+       vt[4] = data_abort_memdetect_handler;
 
        sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-       writel(sz, &digctl_regs->hw_digctl_scratch0);
-       writel(sz, &digctl_regs->hw_digctl_scratch1);
 
        /* Restore the old DABT handler. */
        vt[4] = da;
+
+       return sz;
 }
 
 void mx28_mem_init(void)
@@ -245,6 +247,4 @@ void mx28_mem_init(void)
        early_delay(10000);
 
        mx28_mem_setup_cpu_and_hbus();
-
-       mx28_mem_get_size();
 }