0x00000000, 0x00010001
};
+void __mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+}
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+ __attribute__((weak, alias("__mx28_adjust_memory_params")));
+
void init_m28_200mhz_ddr2(void)
{
int i;
+ mx28_adjust_memory_params(dram_vals);
+
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
/* Disable CPU bypass */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+ early_delay(15000);
}
void mx28_mem_setup_vdda(void)
&power_regs->hw_power_vdddctrl);
}
-void data_abort_memdetect_handler(void) __attribute__((naked));
-void data_abort_memdetect_handler(void)
+uint32_t mx28_mem_get_size(void)
{
- asm volatile("subs pc, r14, #4");
-}
-
-void mx28_mem_get_size(void)
-{
- struct mx28_digctl_regs *digctl_regs =
- (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
uint32_t sz, da;
uint32_t *vt = (uint32_t *)0x20;
+ /* The following is "subs pc, r14, #4", used as return from DABT. */
+ const uint32_t data_abort_memdetect_handler = 0xe25ef004;
/* Replace the DABT handler. */
da = vt[4];
- vt[4] = (uint32_t)&data_abort_memdetect_handler;
+ vt[4] = data_abort_memdetect_handler;
sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- writel(sz, &digctl_regs->hw_digctl_scratch0);
- writel(sz, &digctl_regs->hw_digctl_scratch1);
/* Restore the old DABT handler. */
vt[4] = da;
+
+ return sz;
}
void mx28_mem_init(void)
early_delay(10000);
mx28_mem_setup_cpu_and_hbus();
-
- mx28_mem_get_size();
}