Merge branch 'ext4'

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / mx27 / generic.c

diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
index 27642bfe7dba8a804d21bbbc555c7751d9bb366b..41bb84bb6e7ffe58e64988fc4e88e090daab91fb 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -23,6 +23,8 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
 #ifdef CONFIG_MXC_MMC
 #include <asm/arch/mxcmmc.h>
 #endif
@@ -34,7 +36,7 @@
  *  f = 2 * f_ref * --------------------
  *                        pd + 1
  */
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
 {
        unsigned int mfi = (pll >> 10) & 0xf;
        unsigned int mfn = pll & 0x3ff;
@@ -64,7 +66,7 @@ static ulong clk_in_26m(void)
        }
 }
 
-ulong imx_get_mpllclk(void)
+static ulong imx_get_mpllclk(void)
 {
        struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
        ulong cscr = readl(&pll->cscr);
@@ -78,7 +80,7 @@ ulong imx_get_mpllclk(void)
        return imx_decode_pll(readl(&pll->mpctl0), fref);
 }
 
-ulong imx_get_armclk(void)
+static ulong imx_get_armclk(void)
 {
        struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
        ulong cscr = readl(&pll->cscr);
@@ -93,7 +95,7 @@ ulong imx_get_armclk(void)
        return lldiv(fref, div);
 }
 
-ulong imx_get_ahbclk(void)
+static ulong imx_get_ahbclk(void)
 {
        struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
        ulong cscr = readl(&pll->cscr);
@@ -105,7 +107,7 @@ ulong imx_get_ahbclk(void)
        return lldiv(fref * 2, 3 * div);
 }
 
-ulong imx_get_spllclk(void)
+static __attribute__((unused)) ulong imx_get_spllclk(void)
 {
        struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
        ulong cscr = readl(&pll->cscr);
@@ -124,34 +126,50 @@ static ulong imx_decode_perclk(ulong div)
        return lldiv((imx_get_mpllclk() * 2), (div * 3));
 }
 
-ulong imx_get_perclk1(void)
+static ulong imx_get_perclk1(void)
 {
        struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 
        return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
 }
 
-ulong imx_get_perclk2(void)
+static ulong imx_get_perclk2(void)
 {
        struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 
        return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
 }
 
-ulong imx_get_perclk3(void)
+static __attribute__((unused)) ulong imx_get_perclk3(void)
 {
        struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 
        return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
 }
 
-ulong imx_get_perclk4(void)
+static __attribute__((unused)) ulong imx_get_perclk4(void)
 {
        struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 
        return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
 }
 
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+       switch (clk) {
+       case MXC_ARM_CLK:
+               return imx_get_armclk();
+       case MXC_UART_CLK:
+               return imx_get_perclk1();
+       case MXC_FEC_CLK:
+               return imx_get_ahbclk();
+       case MXC_ESDHC_CLK:
+               return imx_get_perclk2();
+       }
+       return -1;
+}
+
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo (void)
 {
@@ -192,7 +210,7 @@ int cpu_mmc_init(bd_t *bis)
 
 void imx_gpio_mode(int gpio_mode)
 {
-       struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+       struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
        unsigned int pin = gpio_mode & GPIO_PIN_MASK;
        unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
        unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
@@ -211,11 +229,11 @@ void imx_gpio_mode(int gpio_mode)
 
        /* Data direction */
        if (gpio_mode & GPIO_OUT) {
-               writel(readl(&regs->port[port].ddir) | 1 << pin,
-                               &regs->port[port].ddir);
+               writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
+                               &regs->port[port].gpio_dir);
        } else {
-               writel(readl(&regs->port[port].ddir) & ~(1 << pin),
-                               &regs->port[port].ddir);
+               writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
+                               &regs->port[port].gpio_dir);
        }
 
        /* Primary / alternate function */
@@ -271,7 +289,7 @@ void imx_gpio_mode(int gpio_mode)
 }
 
 #ifdef CONFIG_MXC_UART
-void mx27_uart_init_pins(void)
+void mx27_uart1_init_pins(void)
 {
        int i;
        unsigned int mode[] = {
@@ -314,7 +332,7 @@ void mx27_fec_init_pins(void)
                imx_gpio_mode(mode[i]);
 }
 
-void imx_get_mac_from_fuse(unsigned char *mac)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
        int i;
        struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;