Merge git://git.denx.de/u-boot-arc

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / lpc32xx / clk.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index b7a44d59dac31d8c46c8c5fc67a9965b868fc8ad..1ef8a366696d1fc7b0d332333704a5c9d64d636f 100644 (file)
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void)
        return get_hclk_pll_rate() / get_periph_clk_div();
 }
 
+unsigned int get_sdram_clk_rate(void)
+{
+       unsigned int src_clk;
+
+       if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+               return get_sys_clk_rate();
+
+       src_clk = get_hclk_pll_rate();
+
+       if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
+               /* using DDR */
+               switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
+               case CLK_HCLK_DDRAM_HALF:
+                       return src_clk/2;
+               case CLK_HCLK_DDRAM_NOMINAL:
+                       return src_clk;
+               default:
+                       return 0;
+               }
+       } else {
+               /* using SDR */
+               switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
+               case CLK_HCLK_ARM_PLL_DIV_4:
+                       return src_clk/4;
+               case CLK_HCLK_ARM_PLL_DIV_2:
+                       return src_clk/2;
+               case CLK_HCLK_ARM_PLL_DIV_1:
+                       return src_clk;
+               default:
+                       return 0;
+               }
+       }
+}
+
 int get_serial_clock(void)
 {
        return get_periph_clk_rate();