ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / cache.c

diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index ee90ab71958792f5257a304d6db5be589f21d510..7b7eaaf31df8e231059cdabd6ac58ec427c676d6 100644 (file)
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -1,53 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2011
  * Ilya Yanok, EmCraft Systems
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
  */
+#include <cpu_func.h>
 #include <linux/types.h>
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
-static inline void dcache_noop(void)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void invalidate_dcache_all(void)
 {
-       if (dcache_status()) {
-               puts("WARNING: cache operations are not implemented!\n"
-                    "WARNING: disabling D-Cache now, you can re-enable it"
-                    "later with 'dcache on' command\n");
-               dcache_disable();
-       }
+       asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
 }
 
-void invalidate_dcache_all(void)
+void flush_dcache_all(void)
 {
-       dcache_noop();
+       asm volatile(
+               "0:"
+               "mrc p15, 0, r15, c7, c14, 3\n"
+               "bne 0b\n"
+               "mcr p15, 0, %0, c7, c10, 4\n"
+                : : "r"(0) : "memory"
+       );
 }
 
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-       dcache_noop();
+       if (!check_cache_range(start, stop))
+               return;
+
+       while (start < stop) {
+               asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+               start += CONFIG_SYS_CACHELINE_SIZE;
+       }
 }
 
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-       dcache_noop();
+       if (!check_cache_range(start, stop))
+               return;
+
+       while (start < stop) {
+               asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
+               start += CONFIG_SYS_CACHELINE_SIZE;
+       }
+
+       asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -55,16 +55,37 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
+/*
+ * Stub implementations for l2 cache operations
+ */
 
-void flush_dcache_range(unsigned long start, unsigned long stop)
+__weak void l2_cache_disable(void) {}
+
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+__weak void invalidate_l2_cache(void) {}
+#endif
+
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+/* Invalidate entire I-cache and branch predictor array */
+void invalidate_icache_all(void)
 {
+       unsigned long i = 0;
+
+       asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
 }
+#else
+void invalidate_icache_all(void) {}
+#endif
 
-void  flush_cache(unsigned long start, unsigned long size)
+void enable_caches(void)
 {
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+       icache_enable();
+#endif
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+       dcache_enable();
+#endif
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+