ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / cache.c

diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index e86c2edd3bbfa160d22eeb224990b40e4657ae65..7b7eaaf31df8e231059cdabd6ac58ec427c676d6 100644 (file)
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -1,18 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2011
  * Ilya Yanok, EmCraft Systems
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
+#include <cpu_func.h>
 #include <linux/types.h>
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE      32
-#endif
-
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void invalidate_dcache_all(void)
 {
        asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -29,23 +24,6 @@ void flush_dcache_all(void)
        );
 }
 
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
-       int ok = 1;
-
-       if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
-               ok = 0;
-
-       if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
-               ok = 0;
-
-       if (!ok)
-               debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-                       start, stop);
-
-       return ok;
-}
-
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
        if (!check_cache_range(start, stop))
@@ -69,12 +47,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 
        asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -82,24 +55,37 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
+/*
+ * Stub implementations for l2 cache operations
+ */
 
-void flush_dcache_range(unsigned long start, unsigned long stop)
+__weak void l2_cache_disable(void) {}
+
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+__weak void invalidate_l2_cache(void) {}
+#endif
+
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+/* Invalidate entire I-cache and branch predictor array */
+void invalidate_icache_all(void)
 {
+       unsigned long i = 0;
+
+       asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
 }
+#else
+void invalidate_icache_all(void) {}
+#endif
 
-void flush_cache(unsigned long start, unsigned long size)
+void enable_caches(void)
 {
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+       icache_enable();
+#endif
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+       dcache_enable();
+#endif
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
-
-/*
- * Stub implementations for l2 cache operations
- */
-void __l2_cache_disable(void) {}
 
-void l2_cache_disable(void)
-       __attribute__((weak, alias("__l2_cache_disable")));