imx: woodburn: Convert to iomux-v3

[oweals/u-boot.git] / arch / arm / cpu / arm1136 / mx31 / generic.c

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 248431b9bc58ecf60f6d3563ec3954ee9ca28bb5..b9f9b43fa664adae1ee4982e7cc3230c05739ef8 100644 (file)
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -22,35 +22,38 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
+#include <asm/arch/sys_proto.h>
 
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
-       u32 mfi = (reg >> 10) & 0xf;
-       u32 mfn = reg & 0x3ff;
-       u32 mfd = (reg >> 16) & 0x3ff;
-       u32 pd =  (reg >> 26) & 0xf;
+       u32 mfi = GET_PLL_MFI(reg);
+       s32 mfn = GET_PLL_MFN(reg);
+       u32 mfd = GET_PLL_MFD(reg);
+       u32 pd =  GET_PLL_PD(reg);
 
        mfi = mfi <= 5 ? 5 : mfi;
+       mfn = mfn >= 512 ? mfn - 1024 : mfn;
        mfd += 1;
        pd += 1;
 
-       return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
-               (mfd * pd)) << 10;
+       return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+               mfd * pd);
 }
 
 static u32 mx31_get_mpl_dpdgck_clk(void)
 {
        u32 infreq;
 
-       if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
-               infreq = CONFIG_MX31_CLK32 * 1024;
+       if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+               infreq = MXC_CLK32 * 1024;
        else
-               infreq = CONFIG_MX31_HCLK_FREQ;
+               infreq = MXC_HCLK;
 
-       return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
+       return mx31_decode_pll(readl(CCM_MPCTL), infreq);
 }
 
 static u32 mx31_get_mcu_main_clk(void)
@@ -64,10 +67,21 @@ static u32 mx31_get_mcu_main_clk(void)
 static u32 mx31_get_ipg_clk(void)
 {
        u32 freq = mx31_get_mcu_main_clk();
-       u32 pdr0 = __REG(CCM_PDR0);
+       u32 pdr0 = readl(CCM_PDR0);
 
-       freq /= ((pdr0 >> 3) & 0x7) + 1;
-       freq /= ((pdr0 >> 6) & 0x3) + 1;
+       freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
+       freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
+
+       return freq;
+}
+
+/* hsp is the clock for the ipu */
+static u32 mx31_get_hsp_clk(void)
+{
+       u32 freq = mx31_get_mcu_main_clk();
+       u32 pdr0 = readl(CCM_PDR0);
+
+       freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
 
        return freq;
 }
@@ -75,8 +89,9 @@ static u32 mx31_get_ipg_clk(void)
 void mx31_dump_clocks(void)
 {
        u32 cpufreq = mx31_get_mcu_main_clk();
-       printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
+       printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
        printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
+       printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
 }
 
 unsigned int mxc_get_clock(enum mxc_clock clk)
@@ -85,9 +100,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        case MXC_ARM_CLK:
                return mx31_get_mcu_main_clk();
        case MXC_IPG_CLK:
+       case MXC_IPG_PERCLK:
        case MXC_CSPI_CLK:
        case MXC_UART_CLK:
+       case MXC_ESDHC_CLK:
+       case MXC_I2C_CLK:
                return mx31_get_ipg_clk();
+       case MXC_IPU_CLK:
+               return mx31_get_hsp_clk();
        }
        return -1;
 }
@@ -104,10 +124,10 @@ void mx31_gpio_mux(unsigned long mode)
        reg = IOMUXC_BASE + (mode & 0x1fc);
        shift = (~mode & 0x3) * 8;
 
-       tmp = __REG(reg);
+       tmp = readl(reg);
        tmp &= ~(0xff << shift);
        tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
-       __REG(reg) = tmp;
+       writel(tmp, reg);
 }
 
 void mx31_set_pad(enum iomux_pins pin, u32 config)
@@ -118,11 +138,35 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
        reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
        field = (pin + 2) % 3;
 
-       l = __REG(reg);
+       l = readl(reg);
        l &= ~(0x1ff << (field * 10));
        l |= config << (field * 10);
-       __REG(reg) = l;
+       writel(l, reg);
+
+}
+
+void mx31_set_gpr(enum iomux_gp_func gp, char en)
+{
+       u32 l;
+       struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
+
+       l = readl(&iomuxc->gpr);
+       if (en)
+               l |= gp;
+       else
+               l &= ~gp;
+
+       writel(l, &iomuxc->gpr);
+}
+
+void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
+{
+       struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
+       struct mx31_weim_cscr *cscr = &weim->cscr[cs];
 
+       writel(weimcs->upper, &cscr->upper);
+       writel(weimcs->lower, &cscr->lower);
+       writel(weimcs->additional, &cscr->additional);
 }
 
 struct mx3_cpu_type mx31_cpu_type[] = {
@@ -169,17 +213,19 @@ static char *get_reset_cause(void)
                return "WDOG";
        case 0x0006:
                return "JTAG";
+       case 0x0007:
+               return "ARM11P power gating";
        default:
                return "unknown reset";
        }
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
+int print_cpuinfo(void)
 {
        u32 srev = get_cpu_rev();
 
-       printf("CPU:   Freescale i.MX31 rev %d.%d%s at %d MHz.",
+       printf("CPU:   Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
                        (srev & 0xF0) >> 4, (srev & 0x0F),
                        ((srev & 0x8000) ? " unknown" : ""),
                        mx31_get_mcu_main_clk() / 1000000);