config THUMB2_KERNEL
bool
+config SYS_ARM_CACHE_CP15
+ bool "CP15 based cache enabling support"
+ help
+ Select this if your processor suports enabling caches by using
+ CP15 registers.
+
config SYS_ARM_MMU
bool "MMU-based Paged Memory Management Support"
+ select SYS_ARM_CACHE_CP15
help
Select if you want MMU-based virtualised addressing space
support by paged memory management.
+config SYS_ARM_MPU
+ bool 'Use the ARM v7 PMSA Compliant MPU'
+ help
+ Some ARM systems without an MMU have instead a Memory Protection
+ Unit (MPU) that defines the type and permissions for regions of
+ memory.
+ If your CPU has an MPU then you should choose 'y' here unless you
+ know that you do not want to use the MPU.
+
# If set, the workarounds for these ARM errata are applied early during U-Boot
# startup. Note that in general these options force the workarounds to be
# applied; no CPU-type/version detection exists, unlike the similar options in
select HAS_THUMB2
select THUMB2_KERNEL
select SYS_CACHE_SHIFT_5
+ select SYS_ARM_MPU
+
+config CPU_V7R
+ bool
+ select HAS_THUMB2
+ select SYS_CACHE_SHIFT_6
+ select SYS_ARM_MPU
+ select SYS_ARM_CACHE_CP15
config CPU_PXA
bool
default "arm1136" if CPU_ARM1136
default "arm1176" if CPU_ARM1176
default "armv7" if CPU_V7A
+ default "armv7" if CPU_V7R
default "armv7m" if CPU_V7M
default "pxa" if CPU_PXA
default "sa1100" if CPU_SA1100
default 6 if CPU_ARM1176
default 7 if CPU_V7A
default 7 if CPU_V7M
+ default 7 if CPU_V7R
default 5 if CPU_PXA
default 4 if CPU_SA1100
default 8 if ARM64
imply CMD_CLK
imply FAT_WRITE
imply CMD_SPL
+ imply ARCH_EARLY_INIT_R
+
+config ARCH_ZYNQMP_R5
+ bool "Xilinx ZynqMP R5 based platform"
+ select CPU_V7R
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
+ select CLK
config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
source "arch/arm/mach-zynq/Kconfig"
+source "arch/arm/mach-zynqmp-r5/Kconfig"
+
source "arch/arm/cpu/armv7/Kconfig"
source "arch/arm/cpu/armv8/zynqmp/Kconfig"