ARC: [plat-hsdk]: migrate to DM_MMC

[oweals/u-boot.git] / arch / arc / dts / hsdk.dts

diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 5e9ba054a4cc4e24419aa03aea60c7ec2e1d612b..7028050447ba3337e53e6ac2fbd3ce7c9f7de267 100644 (file)
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -86,6 +86,32 @@
                reg = <0xf0060000 0x100>;
        };
 
+       mmcclk_ciu: mmcclk-ciu {
+               compatible = "fixed-clock";
+               /*
+                * DW sdio controller has external ciu clock divider
+                * controlled via register in SDIO IP. Due to its
+                * unexpected default value (it should divide by 1
+                * but it divides by 8) SDIO IP uses wrong clock and
+                * works unstable (see STAR 9001204800)
+                * We switched to the minimum possible value of the
+                * divisor (div-by-2) in HSDK platform code.
+                * So default mmcclk ciu clock is 50000000 Hz.
+                */
+               clock-frequency = <50000000>;
+               #clock-cells = <0>;
+       };
+
+       mmc: mmc0@f000a000 {
+               compatible = "snps,dw-mshc";
+               reg = <0xf000a000 0x400>;
+               bus-width = <4>;
+               fifo-depth = <256>;
+               clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
+               clock-names = "biu", "ciu";
+               max-frequency = <25000000>;
+       };
+
        spi0: spi@f0020000 {
                compatible = "snps,dw-apb-ssi";
                reg = <0xf0020000 0x1000>;