ARC: CACHE: mark IOC helper functions as inlined_cachefunc

[oweals/u-boot.git] / arch / arc / Kconfig

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index a8dc4e2336da12aeef0c696be61267688492d925..545fc3e243cdf0b8c1d05237b84fde3432e2309a 100644 (file)
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -4,34 +4,80 @@ menu "ARC architecture"
 config SYS_ARCH
        default "arc"
 
-config USE_PRIVATE_LIBGCC
-       default y
-
 config SYS_CPU
-       default "arcv1"
+       default "arcv1" if ISA_ARCOMPACT
+       default "arcv2" if ISA_ARCV2
+
+choice
+       prompt "ARC Instruction Set"
+       default ISA_ARCOMPACT
+
+config ISA_ARCOMPACT
+       bool "ARCompact ISA"
+       help
+         The original ARC ISA of ARC600/700 cores
+
+config ISA_ARCV2
+       bool "ARC ISA v2"
+       help
+         ISA for the Next Generation ARC-HS cores
+
+endchoice
 
 choice
        prompt "CPU selection"
-       default CPU_ARC770D
+       default CPU_ARC770D if ISA_ARCOMPACT
+       default CPU_ARCHS38 if ISA_ARCV2
 
 config CPU_ARC750D
        bool "ARC 750D"
+       depends on ISA_ARCOMPACT
        select ARC_MMU_V2
        help
          Choose this option to build an U-Boot for ARC750D CPU.
 
 config CPU_ARC770D
        bool "ARC 770D"
+       depends on ISA_ARCOMPACT
        select ARC_MMU_V3
        help
          Choose this option to build an U-Boot for ARC770D CPU.
 
+config CPU_ARCEM6
+       bool "ARC EM6"
+       depends on ISA_ARCV2
+       select ARC_MMU_ABSENT
+       help
+         Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS36
+       bool "ARC HS36"
+       depends on ISA_ARCV2
+       select ARC_MMU_ABSENT
+       help
+         Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS38
+       bool "ARC HS38"
+       depends on ISA_ARCV2
+       select ARC_MMU_V4
+       help
+         Next Generation ARC Core based on ISA-v2 ISA with MMU.
+
 endchoice
 
 choice
        prompt "MMU Version"
        default ARC_MMU_V3 if CPU_ARC770D
        default ARC_MMU_V2 if CPU_ARC750D
+       default ARC_MMU_ABSENT if CPU_ARCEM6
+       default ARC_MMU_ABSENT if CPU_ARCHS36
+       default ARC_MMU_V4 if CPU_ARCHS38
+
+config ARC_MMU_ABSENT
+       bool "No MMU"
+       help
+         No MMU
 
 config ARC_MMU_V2
        bool "MMU v2"
@@ -48,6 +94,12 @@ config ARC_MMU_V3
          Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
          Shared Address Spaces (SASID)
 
+config ARC_MMU_V4
+       bool "MMU v4"
+       depends on CPU_ARCHS38
+       help
+         Introduced as a part of ARC HS38 release.
+
 endchoice
 
 config CPU_BIG_ENDIAN
@@ -57,40 +109,85 @@ config CPU_BIG_ENDIAN
          Build kernel for Big Endian Mode of ARC CPU
 
 config SYS_ICACHE_OFF
-       bool "Do not use Instruction Cache"
+       bool "Do not enable icache"
        default n
+       help
+         Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+       bool "Do not enable icache in SPL"
+       depends on SPL
+       default SYS_ICACHE_OFF
+       help
+         Do not enable instruction cache in SPL.
 
 config SYS_DCACHE_OFF
-       bool "Do not use Data Cache"
+       bool "Do not enable dcache"
        default n
+       help
+         Do not enable data cache in U-Boot.
 
-config ARC_CACHE_LINE_SHIFT
-       int "Cache Line Length (as power of 2)"
-       range 5 7
-       default "6"
-       depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
+config SPL_SYS_DCACHE_OFF
+       bool "Do not enable dcache in SPL"
+       depends on SPL
+       default SYS_DCACHE_OFF
        help
-         Starting with ARC700 4.9, Cache line length is configurable,
-         This option specifies "N", with Line-len = 2 power N
-         So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
-         Linux only supports same line lengths for I and D caches.
+         Do not enable data cache in SPL.
+
+menuconfig ARC_DBG
+       bool "ARC debugging"
+       default n
+
+if ARC_DBG
+
+config ARC_DBG_IOC_ENABLE
+       bool "Enable IO coherency unit"
+       depends on CPU_ARCHS38
+       default n
+       help
+         Enable IO coherency unit to debug problems with caches and
+         DMA peripherals.
+         NOTE: as of today linux will not work properly if this option
+         is enabled in u-boot!
+
+endif
 
 choice
        prompt "Target select"
+       default TARGET_AXS103
 
 config TARGET_TB100
        bool "Support tb100"
 
-config TARGET_ARCANGEL4
-       bool "Support arcangel4"
+config TARGET_NSIM
+       bool "Support ARC simulation & prototyping platforms"
 
 config TARGET_AXS101
-       bool "Support axs101"
+       bool "Support Synopsys Designware SDP board AXS101"
+       select BOUNCE_BUFFER if CMD_NAND
+
+config TARGET_AXS103
+       bool "Support Synopsys Designware SDP board AXS103"
+       select BOUNCE_BUFFER if CMD_NAND
+
+config TARGET_EMSDP
+       bool "Synopsys EM Software Development Platform"
+       select CPU_ARCEM6
+
+config TARGET_HSDK
+       bool "Support Synpsys HS DevelopmentKit board"
+
+config TARGET_IOT_DEVKIT
+       bool "Synopsys Brite IoT Development kit"
+       select CPU_ARCEM6
 
 endchoice
 
 source "board/abilis/tb100/Kconfig"
-source "board/synopsys/Kconfig"
-source "board/synopsys/axs101/Kconfig"
+source "board/synopsys/axs10x/Kconfig"
+source "board/synopsys/emsdp/Kconfig"
+source "board/synopsys/hsdk/Kconfig"
+source "board/synopsys/iot_devkit/Kconfig"
+source "board/synopsys/nsim/Kconfig"
 
 endmenu