PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
- CONFIG_SPL_FSL_PBL
- It adds a target to create boot binary having SPL binary in PBI format
- concatenated with u-boot binary.
-
CONFIG_SYS_FSL_DDR_BE
Defines the DDR controller register space as Big Endian
the defaults discussed just above.
- Cache Configuration:
- CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
- CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
- Cache Configuration for ARM:
CONFIG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
-- PWM Support:
- CONFIG_PWM_IMX
- Support for PWM module on the imx6.
-
- TPM Support:
CONFIG_TPM
Support TPM devices.
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
- CONFIG_SPL_NAND_BOOT
- Add support NAND boot
-
CONFIG_SYS_NAND_U_BOOT_OFFS
Location in NAND to read U-Boot from
- CONFIG_SYS_FMAN_FW_ADDR
The address in the storage device where the FMAN microcode is located. The
- meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ meaning of this address depends on which CONFIG_SYS_QE_FMAN_FW_IN_xxx macro
is also specified.
- CONFIG_SYS_QE_FW_ADDR
The address in the storage device where the QE microcode is located. The
- meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ meaning of this address depends on which CONFIG_SYS_QE_FMAN_FW_IN_xxx macro
is also specified.
- CONFIG_SYS_QE_FMAN_FW_LENGTH